- 专利标题: DYNAMICALLY ENABLING TILING IN 3D WORKLOADS
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申请号: US17526462申请日: 2021-11-15
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公开(公告)号: US20220148261A1公开(公告)日: 2022-05-12
- 发明人: Justin DeCell , Saurabh Sharma , Subramaniam Maiyuran , Raghavendra Miyar , Jorge Garcia Pabon
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06T17/10
- IPC分类号: G06T17/10 ; G06T17/20 ; G06T1/20 ; G06T15/00
摘要:
Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
公开/授权文献
- US11640693B2 Dynamically enabling tiling in 3D workloads 公开/授权日:2023-05-02
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