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公开(公告)号：US20240185527A1
公开(公告)日：2024-06-06
申请号：US18409753
申请日：2024-01-10
申请人： Intel Corporation
发明人： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
CPC分类号： G06T17/20 , G06T1/20 , G06T15/005
摘要： An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
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公开(公告)号：US11615584B2
公开(公告)日：2023-03-28
申请号：US17382888
申请日：2021-07-22
申请人： Intel Corporation
发明人： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker , Prasoonkumar Surti , Abhishek Appu , Joydeep Ray , Art Hunter , Luis F. Cruz Camacho , Akshay R. Chada
摘要： Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
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公开(公告)号：US11494867B2
公开(公告)日：2022-11-08
申请号：US17115555
申请日：2020-12-08
申请人： Intel Corporation
发明人： Saurabh Sharma , Michael Apodaca , Aditya Navale , Travis Schluessler , Vamsee Vardhan Chivukula , Abhishek Venkatesh , Subramaniam Maiyuran
IPC分类号： G06T1/20
摘要： An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.
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公开(公告)号：US11250627B2
公开(公告)日：2022-02-15
申请号：US16914783
申请日：2020-06-29
申请人： Intel Corporation
发明人： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
摘要： An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
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公开(公告)号：US10769751B2
公开(公告)日：2020-09-08
申请号：US16543849
申请日：2019-08-19
申请人： Intel Corporation
发明人： Subramaniam Maiyuran , Jorge F. Garcia Pabon , Vikranth Vemulapalli , Chandra S. Gurram , Aditya Navale , Saurabh Sharma
摘要： A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a register file having a plurality of channels to store data and an execution unit to examine data at each of the plurality of channels, read a data value from a first of the plurality of channels upon a determination that each of the plurality of channels has the same data and execute a single input multi data (SIMD) instruction based on the data value.
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公开(公告)号：US10424107B2
公开(公告)日：2019-09-24
申请号：US15477049
申请日：2017-04-01
申请人： Intel Corporation
发明人： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker , Prasoonkumar Surti , Abhishek Appu , Joydeep Ray , Art Hunter , Luis F. Cruz Camacho , Akshay R. Chada
摘要： Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
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公开(公告)号：US20190272613A1
公开(公告)日：2019-09-05
申请号：US16279270
申请日：2019-02-19
申请人： Intel Corporation
发明人： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
摘要： A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US20190251655A1
公开(公告)日：2019-08-15
申请号：US16388098
申请日：2019-04-18
申请人： Intel Corporation
发明人： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
CPC分类号： G06T1/20 , G06T1/60 , G06T15/005
摘要： A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US20190026855A1
公开(公告)日：2019-01-24
申请号：US16046650
申请日：2018-07-26
申请人： Intel Corporation
发明人： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC分类号： G06T1/60 , G06T1/20 , G06F12/0875
CPC分类号： G06T1/60 , G06F12/0875 , G06F2212/455 , G06T1/20
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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公开(公告)号：US11900539B2
公开(公告)日：2024-02-13
申请号：US17590521
申请日：2022-02-01
申请人： Intel Corporation
发明人： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
CPC分类号： G06T17/20 , G06T1/20 , G06T15/005
摘要： An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
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