Invention Application
- Patent Title: PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE
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Application No.: US17585082Application Date: 2022-01-26
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Publication No.: US20220148968A1Publication Date: 2022-05-12
- Inventor: Andrew COLLINS , Bharat P. PENMECHA , Rajasekaran SWAMINATHAN , Ram VISWANATH
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/538 ; H01L23/498 ; H01L23/00 ; H01L25/065 ; H01L25/18

Abstract:
Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.
Public/Granted literature
- US11705398B2 Pitch translation architecture for semiconductor package including embedded interconnect bridge Public/Granted day:2023-07-18
Information query
IPC分类: