公开(公告)号：US20150194401A1

公开(公告)日：2015-07-09

申请号：US14658089

申请日：2015-03-13

Applicant: INTEL CORPORATION

Inventor： Rajasekaran SWAMINATHAN ,  Leonel R. ARANA ,  Yoshihiro TOMITA ,  Yosuke KANAOKA

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Abstract translation: 描述形成微电子封装结构的方法。 这些方法可以包括在衬底上形成包含牺牲聚合物的焊膏，将焊膏固化在焊料的回流温度以下，以在导电焊盘上形成固体复合混合凸块，在固体复合混合凸块周围形成模塑料， 并且回流混合凸块，其中牺牲聚合物基本分解。

公开(公告)号：US20240030086A1

公开(公告)日：2024-01-25

申请号：US18376341

申请日：2023-10-03

Applicant: Intel Corporation

Inventor： Rajasekaran SWAMINATHAN ,  Mukul RENAVIKAR

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/3736 ,  H01L24/09 ,  H01L24/17 ,  H01L24/06 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01047 ,  H01L2924/15311

Abstract: Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.

公开(公告)号：US20230138543A1

公开(公告)日：2023-05-04

申请号：US18091982

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20200235051A1

公开(公告)日：2020-07-23

申请号：US16839393

申请日：2020-04-03

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20200066641A1

公开(公告)日：2020-02-27

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Richard J. DISCHLER ,  Jeff C. MORRISS ,  Zhiguo QIAN ,  Wilfred GOMES ,  Yu Amos ZHANG ,  Ram S. VISWANATH ,  Rajasekaran SWAMINATHAN ,  Sriram SRINIVASAN ,  Yidnekachew S. MEKONNEN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Mathew J. MANUSHAROW

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/60

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

公开(公告)号：US20230352412A1

公开(公告)日：2023-11-02

申请号：US18221184

申请日：2023-07-12

Applicant: Intel Corporation

Inventor： Yidnekachew S. MEKONNEN ,  Kemel AYGUN ,  Ravindranath V. MAHAJAN ,  Christopher S. BALDWIN ,  Rajasekaran SWAMINATHAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/14 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/145 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235

Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

公开(公告)号：US20220344247A1

公开(公告)日：2022-10-27

申请号：US17862300

申请日：2022-07-11

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20220148968A1

公开(公告)日：2022-05-12

申请号：US17585082

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20240347457A1

公开(公告)日：2024-10-17

申请号：US18750571

申请日：2024-06-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5283 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20240030116A1

公开(公告)日：2024-01-25

申请号：US18375133

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/29

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.