公开(公告)号：US20250070030A1

公开(公告)日：2025-02-27

申请号：US18943420

申请日：2024-11-11

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Ram VISWANATH ,  Xavier Francois BRUN ,  Tarek A. IBRAHIM ,  Jason M. GAMBA ,  Manish DUBEY ,  Robert Alan MAY

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20200235051A1

公开(公告)日：2020-07-23

申请号：US16839393

申请日：2020-04-03

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20220148968A1

公开(公告)日：2022-05-12

申请号：US17585082

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20190103349A1

公开(公告)日：2019-04-04

申请号：US15721844

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Ram VISWANATH ,  Srikant NEKKANTY

IPC: H01L23/50 ,  H01L23/34 ,  H01R13/24 ,  H05K3/30

Abstract: An apparatus is provided which comprises: a substrate material comprising one or more embedded copper planes, one or more plated through holes through the substrate material, one or more metal contacts, the metal contacts comprising a substantially straight section coupled with adhesive within the one or more plated through holes, and a cantilever spring section extending beyond a first surface of the substrate material, and one or more conductive contacts on a second surface of the substrate material, opposite the first surface, the conductive contacts coupled with the metal contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240347457A1

公开(公告)日：2024-10-17

申请号：US18750571

申请日：2024-06-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5283 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20230290728A1

公开(公告)日：2023-09-14

申请号：US18199735

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5283 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.