Invention Application
- Patent Title: INTEGRATED CIRCUIT WITH MIXED ROW HEIGHTS
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Application No.: US17585402Application Date: 2022-01-26
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Publication No.: US20220149033A1Publication Date: 2022-05-12
- Inventor: Kam-Tou SIO , Jiann-Tyng TZENG , Chung-Hsing WANG , Yi-Kan CHENG
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu City
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu City
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/092

Abstract:
An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.
Public/Granted literature
- US11769766B2 Integrated circuit with mixed row heights Public/Granted day:2023-09-26
Information query
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