公开(公告)号：US20230246016A1

公开(公告)日：2023-08-03

申请号：US18191702

申请日：2023-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Sang-Chi HUANG

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/398 ,  G06F30/31 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/398 ,  G06F30/31 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/5228 ,  H01L27/0922 ,  H01L29/42376 ,  G06F2119/18

Abstract: A semiconductor structure is disclosed, including a first gate and a second gate aligned with the first gate, a first gate via, a second gate via, multiple conductive segments, and a first conductive line. The first gate via is disposed on the first gate and the second gate via is disposed on the second gate. The first and second gates are configured to be a terminal of a first logic circuit, which is coupled to a terminal of a second logic circuit. The first conductive line is coupled to the first gate through a first connection via and the first gate via and is electrically coupled to the second gate through a second connection via and the second gate via.

公开(公告)号：US20210391328A1

公开(公告)日：2021-12-16

申请号：US16900768

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG

IPC: H01L27/092 ,  G06F30/392

Abstract: An IC structure includes first and second cell rows extending in a first direction. The first cell row includes first cells each including one or more first fins having first source/drain regions of a first conductivity type and one or more second fins having second source/drain regions of a second conductivity type opposite the first conductivity type. The second cell row includes second cells each including one or more third fins having third source/drain regions of the first conductivity type and one or more fourth fins having fourth source/drain regions of the second conductivity type. The first cells have a same first number of the one or more first fins, and the second cells have a same second number of the one or more third fins less than the first number of the one or more first fins.

公开(公告)号：US20210082903A1

公开(公告)日：2021-03-18

申请号：US17092100

申请日：2020-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394

Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US20190164949A1

公开(公告)日：2019-05-30

申请号：US16196434

申请日：2018-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng Tzeng ,  Jack Liu ,  Yi-Chuin Tsai ,  Shang-Wei Fang ,  Sing-Kai Huang

IPC: H01L27/02 ,  H01L27/118 ,  G06F17/50

Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.

公开(公告)号：US20160172297A1

公开(公告)日：2016-06-16

申请号：US15050087

申请日：2016-02-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Yung-Sung YEN ,  Kam-Tou SIO ,  Tsong-Hua OU ,  Chun-Kuang CHEN ,  Ru-Gun LIU ,  Shu-Hui SUNG ,  Charles Chew-Yuen YOUNG

IPC: H01L23/528 ,  H01L27/118 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2   P gate   min + 0.35   L gate   min + 0.3   H gate   min - 20 0.2   L gate   min + 0.8   H gate   min - 5 × 0.3   L gate   min + 0.3   H gate   min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

Abstract translation: 提供半导体结构。 半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构。 门结构遵循以下公式：0.2P门min + 0.35min min min min 最小 - 5×0.3英尺L门槛最小+ 0.3H门min + 5 38≤0.32 Pgate min是栅极结构的栅间距中的最小值，Lgate min是 栅极结构的栅极长度。 Hgate min是门结构栅极高度的最小值。

公开(公告)号：US20230113294A1

公开(公告)日：2023-04-13

申请号：US18064910

申请日：2022-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/423 ,  H01L29/66

Abstract: A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.

公开(公告)号：US20210118793A1

公开(公告)日：2021-04-22

申请号：US17133264

申请日：2020-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L49/02 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively. A length of the first conductive segment is greater than a length of the third conductive segment.

公开(公告)号：US20180151567A1

公开(公告)日：2018-05-31

申请号：US15457640

申请日：2017-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng LIN ,  Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG

IPC: H01L27/092 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/768

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807

Abstract: A semiconductor device includes an active region comprising a source/drain region and a plurality of poly strips spaced apart and arranged along a first direction crossing over the active region. The first direction is substantially perpendicular to a lengthwise direction of the active region. A first metal pattern is disposed on the poly strips and arranged along the first direction. A plurality of first interconnect plugs is interposed in between the poly strips and the first metal pattern and in between the active region and the first metal pattern. A position of the first interconnect plugs being variable along the first direction.

公开(公告)号：US20170256484A1

公开(公告)日：2017-09-07

申请号：US15058077

申请日：2016-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L29/423 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/762 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L28/00 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/01029

Abstract: A semiconductor structure is disclosed that includes a semiconductor structure includes an active area, a first conductive line, a conductive via, a first conductive metal segment coupled to the conductive line through the conductive via, a second conductive metal segment disposed over the active area, and a local conductive segment configured to couple the first conductive metal segment and the second conductive metal segment.

公开(公告)号：US20250167108A1

公开(公告)日：2025-05-22

申请号：US19030702

申请日：2025-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H10D1/00 ,  H10D30/01 ,  H10D30/62 ,  H10D64/27 ,  H10D84/83 ,  H10D84/85 ,  H10D89/10

Abstract: A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.