TECHNOLOGIES FOR A PROCESSOR TO ENTER A REDUCED POWER STATE WHILE MONITORING MULTIPLE ADDRESSES
Abstract:
Examples described herein relate to circuitry to cause a processor to enter reduced power consumption state and circuitry to, based on a write to one or more of multiple memory regions, cause the processor to exit reduced power consumption state, wherein the multiple memory regions store receive descriptors associated with one or more packets received by a network interface device. In some examples, multiple memory regions are defined by a driver of the network interface device. In some examples, the reduced power consumption state comprises a TPAUSE state.
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