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1.
公开(公告)号:US20190114196A1
公开(公告)日:2019-04-18
申请号:US16211950
申请日:2018-12-06
Applicant: Intel Corporation
Inventor: Mitu AGGARWAL , Nrupal JANI , Manasi DEVAL , Kiran PATIL , Parthasarathy SARANGAM , Rajesh M. SANKARAN , Sanjay K. KUMAR , Utkarsh Y. KAKAIYA , Philip LANTZ , Kun TIAN
Abstract: Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.
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2.
公开(公告)号:US20190107965A1
公开(公告)日:2019-04-11
申请号:US16211930
申请日:2018-12-06
Applicant: Intel Corporation
Inventor: Manasi DEVAL , Nrupal JANI , Parthasarathy SARANGAM , Mitu AGGARWAL , Kiran PATIL , Rajesh M. SANKARAN , Sanjay K. KUMAR , Utkarsh Y. KAKAIYA , Philip LANTZ , Kun TIAN
Abstract: Examples may include a method of protecting memory and I/O transactions. The method includes allocating memory for an application, assigning a resource of a physical device to the application, assigning a process address space identifier to the assigned resource, creating a security enclave to protect the allocated memory of the application, and associating the security enclave with the process address space identifier to protect the allocated memory and the assigned resource.
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公开(公告)号:US20250123881A1
公开(公告)日:2025-04-17
申请号:US18927065
申请日:2024-10-25
Applicant: Intel Corporation
Inventor: Rajesh M. SANKARAN , Gilbert NEIGER , Narayan RANGANATHAN , Stephen R. VAN DOREN , Joseph NUZMAN , Niall D. MCDONNELL , Michael A. O'HANLON , Lokpraveen B. MOSUR , Tracy Garrett DRYSDALE , Eriko NURVITADHI , Asit K. MISHRA , Ganesh VENKATESH , Deborah T. MARR , Nicholas P. CARTER , Jonathan D. PEARCE , Edward T. GROCHOWSKI , Richard J. GRECO , Robert VALENTINE , Jesus CORBAL , Thomas D. FLETCHER , Dennis R. BRADFORD , Dwight P. MANLEY , Mark J. CHARNEY , Jeffry J. COOK , Paul CAPRIOLI , Koichi YAMADA , Kent D. GLOSSOP , David B. SHEFFIELD
Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
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公开(公告)号:US20220261178A1
公开(公告)日:2022-08-18
申请号:US17688710
申请日:2022-03-07
Applicant: Intel Corporation
Inventor: Shaopeng HE , Yadong LI , Anjali Singhai JAIN , Kun TIAN , Yan ZHAO , Yaozu DONG , Baolu LU , Rajesh M. SANKARAN , Eliel LOUZOUN , Rupin H. VAKHARWALA , David HARRIMAN , Saurabh GAYEN , Philip LANTZ , Israel BEN SHAHAR , Kenneth G. KEELS
Abstract: Examples described herein relate to a packet processing device that includes circuitry to receive an address translation for a virtual to physical address prior to receipt of a GPUDirect remote direct memory access (RDMA) operation, wherein the address translation is provided at initiation of a process executed by a host system and circuitry to apply the address translation for a received GPUDirect RDMA operation.
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公开(公告)号:US20210117244A1
公开(公告)日:2021-04-22
申请号:US17134327
申请日:2020-12-26
Applicant: Intel Corporation
Inventor: Andrew J. HERDRICH , Priya AUTEE , Rajesh M. SANKARAN , Gilbert NEIGER , Scott OEHRLEIN , Michael PRINKE , Ravi IYER , Edwin VERPLANKE
Abstract: Examples provide a system that includes one or more processors, that when operational, are to: based on content in a request being within a permitted range for a virtualized execution environment, transfer the request from the virtualized execution environment to reserve one or more device resources independent from causing a virtual machine exit to request to reserve one or more device resources. In some examples, the transfer comprises a write to a register. In some examples, processor-executed microcode is to determine whether content in the request is within a permitted range for the virtualized execution environment.
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公开(公告)号:US20190297015A1
公开(公告)日:2019-09-26
申请号:US16435328
申请日:2019-06-07
Applicant: Intel Corporation
Inventor: Pratik M. MAROLIA , Rajesh M. SANKARAN , Ashok RAJ , Nrupal JANI , Parthasarathy SARANGAM , Robert O. SHARP
IPC: H04L12/747 , G06F13/28 , H04L12/773 , G06F12/1081 , H04L12/861
Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.
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公开(公告)号:US20240314072A1
公开(公告)日:2024-09-19
申请号:US18417570
申请日:2024-01-19
Applicant: Intel Corporation
Inventor: Pratik M. MAROLIA , Rajesh M. SANKARAN , Ashok RAJ , Nrupal JANI , Parthasarathy SARANGAM , Robert O. SHARP
IPC: H04L45/74 , G06F12/1081 , G06F13/28 , H04L45/60 , H04L49/90
CPC classification number: H04L45/742 , G06F12/1081 , G06F13/28 , H04L45/60 , H04L49/9068
Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.
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公开(公告)号:US20230418655A1
公开(公告)日:2023-12-28
申请号:US18207870
申请日:2023-06-09
Applicant: Intel Corporation
Inventor: Rajesh M. SANKARAN , Gilbert NEIGER , Narayan RANGANATHAN , Stephen R. VAN DOREN , Joseph NUZMAN , Niall D. MCDONNELL , Michael A. O'HANLON , Lokpraveen B. MOSUR , Tracy Garrett DRYSDALE , Eriko NURVITADHI , Asit K. MISHRA , Ganesh VENKATESH , Deborah T. MARR , Nicholas P. CARTER , Jonathan D. PEARCE , Edward T. GROCHOWSKI , Richard J. GRECO , Robert VALENTINE , Jesus CORBAL , Thomas D. FLETCHER , Dennis R. BRADFORD , Dwight P. MANLEY , Mark J. CHARNEY , Jeffrey J. COOK , Paul CAPRIOLI , Koichi YAMADA , Kent D. GLOSSOP , David B. SHEFFIELD
CPC classification number: G06F9/48 , G06F9/3001 , G06F9/383 , G06F9/3004 , G06F9/30036
Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
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公开(公告)号:US20220350499A1
公开(公告)日:2022-11-03
申请号:US17745453
申请日:2022-05-16
Applicant: Intel Corporation
Inventor: Shaopeng HE , Yadong LI , Anjali Singhai JAIN , Kenneth G. KEELS , Andrzej SAWULA , Kun TIAN , Ashok RAJ , Rupin H. VAKHARWALA , Rajesh M. SANKARAN , Saurabh GAYEN , Baolu LU , Yan ZHAO
Abstract: As described herein, for a selected process identifier and virtual address, a page fault arising from multiple sources can be solved by a one-time operation. The selected process identifier can include a virtual function (VF) identifier or process address space identifier (PASID). In some examples, solving a page fault arising from multiple sources by a one-time operation comprises invoking a page fault handler to determine an address translation.
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公开(公告)号:US20220164218A1
公开(公告)日:2022-05-26
申请号:US17381521
申请日:2021-07-21
Applicant: Intel Corporation
Inventor: Rajesh M. SANKARAN , Gilbert NEIGER , Narayan RANGANATHAN , Stephen R. VAN DOREN , Joseph NUZMAN , Niall D. MCDONNELL , Michael A. O'HANLON , Lokpraveen B. MOSUR , Tracy Garrett DRYSDALE , Eriko NURVITADHI , Asit K. MISHRA , Ganesh VENKATESH , Deborah T. MARR , Nicholas P. CARTER , Jonathan D. PEARCE , Edward T. GROCHOWSKI , Richard J. GRECO , Robert VALENTINE , Jesus CORBAL , Thomas D. FLETCHER , Dennis R. BRADFORD , Dwight P. MANLEY , Mark J. CHARNEY , Jeffrey J. COOK , Paul CAPRIOLI , Koichi YAMADA , Kent D. GLOSSOP , David B. SHEFFIELD
Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
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