Invention Application
- Patent Title: MULTIPLE MEMORY TYPE SHARED MEMORY BUS SYSTEMS AND METHODS
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Application No.: US17682908Application Date: 2022-02-28
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Publication No.: US20220188250A1Publication Date: 2022-06-16
- Inventor: David Andrew Roberts , Joseph Thomas Pawlowski , Elliott Cooper-Balis
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F3/06 ; G06F1/324 ; G06F1/10

Abstract:
Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.
Public/Granted literature
- US11775458B2 Multiple memory type shared memory bus systems and methods Public/Granted day:2023-10-03
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