公开(公告)号：US20240134566A1

公开(公告)日：2024-04-25

申请号：US17972822

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Haojie Ye ,  David Andrew Roberts

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0679

Abstract: Devices and techniques for continuous in-memory versioning are described herein. A memory subsystem includes a memory device configured to store a first data unit, a second data unit, and a third data unit, wherein the first, second, and third data units have a set of physical memory locations on the memory device, and metadata associated with the first, second, and third data units, the metadata including state information and a dirty commit timestamp; and a processing device, operatively coupled to the memory device, the processing device configured to: receive, from a host system, a first memory command associated with a logical memory address, the logical memory address mapped to the set of physical memory locations of the memory device; and in response to receiving the first memory command, perform a data operation on the first, second, or third data unit based on the state information and the dirty commit timestamp.

公开(公告)号：US11775458B2

公开(公告)日：2023-10-03

申请号：US17682908

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski ,  Elliott Cooper-Balis

IPC: G06F13/16 ,  G06F1/10 ,  G06F3/06 ,  G06F1/324

CPC classification number: G06F13/1689 ,  G06F1/10 ,  G06F1/324 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/0685 ,  G06F13/1694

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

公开(公告)号：US20230169011A1

公开(公告)日：2023-06-01

申请号：US18057628

申请日：2022-11-21

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0895 ,  G06F12/0862

CPC classification number: G06F12/0895 ,  G06F12/0862 ,  G06F2212/282 ,  G06F2212/602 ,  G06F2212/1021

Abstract: Described apparatuses and methods partition a cache memory based, at least in part, on a metric indicative of prefetch performance. The amount of cache memory allocated for metadata related to prefetch operations versus cache storage can be adjusted based on operating conditions. Thus, the cache memory can be partitioned into a first portion allocated for metadata pertaining to an address space (prefetch metadata) and a second portion allocated for data associated with the address space (cache data). The amount of cache memory allocated to the first portion can be increased under workloads that are suitable for prefetching and decreased otherwise. The first portion may include one or more cache units, cache lines, cache ways, cache sets, or other resources of the cache memory.

公开(公告)号：US11379376B2

公开(公告)日：2022-07-05

申请号：US16879688

申请日：2020-05-20

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F11/10 ,  G11C5/06 ,  G06F12/0882 ,  G06F12/0868 ,  G06F9/54 ,  G06F11/30 ,  G06F9/50 ,  G01R31/317

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

公开(公告)号：US11334260B2

公开(公告)日：2022-05-17

申请号：US17070815

申请日：2020-10-14

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: Described apparatuses and methods control a voltage or a temperature of a memory domain to balance memory performance and energy use. In some aspects, an adaptive controller monitors memory performance metrics of a host processor that correspond to commands made to a memory domain of a memory system, including one operating at cryogenic temperatures. Based on the memory performance metrics, the adaptive controller can determine memory performance demand of the host processor, such as latency demand or bandwidth demand, for the memory domain. The adaptive controller may alter, using the determined performance demand, a voltage or a temperature of the memory domain to enable memory access performance that is tailored to meet the demand of the host processor. By so doing, the adaptive controller can manage various settings of the memory domain to address short- or long-term changes in memory performance demand.

公开(公告)号：US20220129196A1

公开(公告)日：2022-04-28

申请号：US17082947

申请日：2020-10-28

Applicant: Micron Technology, Inc

Inventor： David Andrew Roberts ,  Sean Stephen Eilert

IPC: G06F3/06 ,  G06F12/06

Abstract: Various embodiments enable versioning of data stored on a memory device, where the versioning allows the memory device to maintain different versions of data within a set of physical memory locations (e.g., a row) of the memory device. In particular, some embodiments provide for a memory device or a memory sub-system that uses versioning of stored data to facilitate a rollback operation/behavior, a checkpoint operation/behavior, or both. Additionally, some embodiments provide for a transactional memory device or a transactional memory sub-system that uses versioning of stored data to enable rollback of a memory transaction, commitment of a memory transaction, or handling of a read or write command associated with respect to a memory transaction.

公开(公告)号：US20210390053A1

公开(公告)日：2021-12-16

申请号：US16901890

申请日：2020-06-15

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F12/0873 ,  G06F12/06 ,  G06F9/30 ,  G06F9/50 ,  G06F9/54 ,  G06N3/04

Abstract: Methods, apparatuses, and techniques related to a host-assisted memory-side prefetcher are described herein. In general, prefetchers monitor the pattern of memory-address requests by a host device and use the pattern information to determine or predict future memory-address requests and fetch data associated with those predicted requests into a faster memory. In many cases, prefetchers that can make predictions with high performance use appreciable processing and computing resources, power, and cooling. Generally, however, producing a prefetching configuration that the prefetcher uses involves more resources than making predictions. The described host-assisted memory-side prefetcher uses the greater computing resources of the host device to produce at least an updated prefetching configuration. The memory-side prefetcher uses the prefetching configuration to predict the data to prefetch into the faster memory, which allows a higher-performance prefetcher to be implemented in the memory device with a reduced resource burden on the memory device.

公开(公告)号：US12236125B2

公开(公告)日：2025-02-25

申请号：US17661244

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: Methods, systems, and devices for performance monitoring for a memory system are described. A memory system may use a set of counters to determine state information for the memory system. The memory system may also use a set of timers to determine latency information for the memory system. In response to a request for performance information, the memory system may transmit state information, latency information, or both to a host system.

公开(公告)号：US20250060888A1

公开(公告)日：2025-02-20

申请号：US18774054

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: To implement a multi-format data object in memory, a device can receive an allocation request for a data object that includes a set of data elements. This allocation request includes respective details for a set of formats for the data object, such as details for a first format in the set of formats including. The details can include memory address information and a mapping between a first data element of the data object in the first format to a second data element in a second format in the set of formats. The details can also include identification of a conversion function configured to convert the first data element to the second data element. The device can provide access to the second format of the data object from the first format of the data object in the memory based on the mapping data structure or the conversion data structure.

公开(公告)号：US12175127B2

公开(公告)日：2024-12-24

申请号：US17831270

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Nabeel Meeramohideen Mohamed ,  Steven Andrew Moyer ,  David Andrew Roberts

IPC: G06F3/06

Abstract: Methods, systems, and devices for access heatmap generation at a memory device are described. In some examples, a memory device may maintain a register for tracking access operation occurrence, for which access operations of an address of the memory device may be mapped to multiple fields of the register. In some cases, in response to a first access operation performed on a first address of the memory device, the memory device may increment a first field and a second field of the register and, in response to a second access operation performed on a second address of the memory device, the memory device may increment the first field and a third field of the register. In some examples, the memory device may maintain a second register having a set of fields that each indicate a respective address for which an access occurrence satisfies a threshold.