公开(公告)号：US11775458B2

公开(公告)日：2023-10-03

申请号：US17682908

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski ,  Elliott Cooper-Balis

IPC: G06F13/16 ,  G06F1/10 ,  G06F3/06 ,  G06F1/324

CPC classification number: G06F13/1689 ,  G06F1/10 ,  G06F1/324 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/0685 ,  G06F13/1694

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

公开(公告)号：US11720439B2

公开(公告)日：2023-08-08

申请号：US17562244

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for media scrubber operations in a memory system are described. A controller may, for example, count a quantity of forwarded code words in a memory medium during a scrubbing period. The controller may add the quantity to a total quantity of forwarded code words in the memory medium. The controller may refrain from forwarding additional code words based on the quantity. The controller may write a valid logic state to a spare bit when the spare bit is assigned to an erroneous bit in a code word. A separate memory cell may indicate a change in spare bit assignments and whether spare bits include valid logic states. The controller may retrieve a code word from a memory medium and invert one or more bits of the code word before writing the code word to the memory medium.

公开(公告)号：US20230169011A1

公开(公告)日：2023-06-01

申请号：US18057628

申请日：2022-11-21

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0895 ,  G06F12/0862

CPC classification number: G06F12/0895 ,  G06F12/0862 ,  G06F2212/282 ,  G06F2212/602 ,  G06F2212/1021

Abstract: Described apparatuses and methods partition a cache memory based, at least in part, on a metric indicative of prefetch performance. The amount of cache memory allocated for metadata related to prefetch operations versus cache storage can be adjusted based on operating conditions. Thus, the cache memory can be partitioned into a first portion allocated for metadata pertaining to an address space (prefetch metadata) and a second portion allocated for data associated with the address space (cache data). The amount of cache memory allocated to the first portion can be increased under workloads that are suitable for prefetching and decreased otherwise. The first portion may include one or more cache units, cache lines, cache ways, cache sets, or other resources of the cache memory.

公开(公告)号：US20220414005A1

公开(公告)日：2022-12-29

申请号：US17861018

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F12/06 ,  G06F11/10

Abstract: Methods, systems, and devices for forwarding a code word address are described. A memory subsystem, for example, may configure a code word including user data as a forwarded code word when the code word becomes unreliable or invalid close to or beyond an error recovery capability of the memory subsystem. The memory subsystem may configure the forwarded code word using a forwarded code word format and structure, which may include a bit field in the forwarded code word to indicate a code word condition and to store a quantity of duplicates of a forwarding address. When the memory subsystem receives a code word, the memory system may determine the code word as a forwarded code word such that the memory system may determine a forwarding address (e.g., from the code word). The memory subsystem may then use the forwarding address to access user data.

公开(公告)号：US20200034228A1

公开(公告)日：2020-01-30

申请号：US16516936

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods, systems, and devices for media scrubber operations in a memory system are described. A controller may, for example, count a quantity of forwarded code words in a memory medium during a scrubbing period. The controller may add the quantity to a total quantity of forwarded code words in the memory medium. The controller may refrain from forwarding additional code words based on the quantity. The controller may write a valid logic state to a spare bit when the spare bit is assigned to an erroneous bit in a code word. A separate memory cell may indicate a change in spare bit assignments and whether spare bits include valid logic states. The controller may retrieve a code word from a memory medium and invert one or more bits of the code word before writing the code word to the memory medium.

公开(公告)号：US11768770B2

公开(公告)日：2023-09-26

申请号：US17823480

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski ,  Elliott Clifford Cooper-Balis ,  David Andrew Roberts

IPC: G06F12/0864 ,  G06F12/084 ,  G06F12/0853 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F12/084 ,  G06F9/30047 ,  G06F9/30101 ,  G06F12/0284 ,  G06F12/0853 ,  G06F12/0864 ,  G06F13/1689 ,  G06F2212/1021

Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

公开(公告)号：US11693775B2

公开(公告)日：2023-07-04

申请号：US17657922

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/0864

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/1044

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

公开(公告)号：US20230061668A1

公开(公告)日：2023-03-02

申请号：US17823480

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski ,  Elliott Clifford Cooper-Balis ,  David Andrew Roberts

IPC: G06F12/084 ,  G06F12/0853 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16 ,  G06F12/0864

Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

公开(公告)号：US11386003B2

公开(公告)日：2022-07-12

申请号：US17071779

申请日：2020-10-15

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F12/06 ,  G06F11/10

Abstract: Methods, systems, and devices for forwarding a code word address are described. A memory subsystem, for example, may configure a code word including user data as a forwarded code word when the code word becomes unreliable or invalid close to or beyond an error recovery capability of the memory subsystem. The memory subsystem may configure the forwarded code word using a forwarded code word format and structure, which may include a bit field in the forwarded code word to indicate a code word condition and to store a quantity of duplicates of a forwarding address. When the memory subsystem receives a code word, the memory system may determine the code word as a forwarded code word such that the memory system may determine a forwarding address (e.g., from the code word). The memory subsystem may then use the forwarding address to access user data.

公开(公告)号：US20210318958A1

公开(公告)日：2021-10-14

申请号：US16846266

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski ,  Elliott Clifford Cooper-Balis ,  David Andrew Roberts

IPC: G06F12/084 ,  G06F12/0853 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16

Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.