Invention Application
- Patent Title: METHODS TO ELIMINATE OF DEPOSITION ON WAFER BEVEL AND BACKSIDE
-
Application No.: US17127201Application Date: 2020-12-18
-
Publication No.: US20220199373A1Publication Date: 2022-06-23
- Inventor: Venkata Sharat Chandra Parimi , Zubin Huang , Manjunath Veerappa Chobari Patil , Nitin Pathak , Yi Yang , Badri N. Ramamurthi , Truong Van Nguyen , Rui Cheng , Diwakar Kedlaya
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01J37/32
- IPC: H01J37/32 ; C23C16/50 ; C23C16/458 ; C23C16/44

Abstract:
Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.
Information query