Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.