公开(公告)号：US20210305138A1

公开(公告)日：2021-09-30

申请号：US16828466

申请日：2020-03-24

申请人： Intel Corporation

发明人： Zhichao ZHANG ,  Zhenguo JIANG ,  Haifa HARIRI ,  Kemal AYGÜN ,  Sriram SRINIVASAN

IPC分类号： H01L23/498 ,  H01R12/71

摘要： Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end.

公开(公告)号：US20220199600A1

公开(公告)日：2022-06-23

申请号：US17132976

申请日：2020-12-23

申请人： Intel Corporation

发明人： Zhichao ZHANG ,  Kemal AYGÜN ,  Suresh V. POTHUKUCHI ,  Xiaoqian LI ,  Omkar KARHADE

IPC分类号： H01L25/18 ,  H01L25/00 ,  G02B6/42

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

申请人： Intel Corporation

发明人： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC分类号： G02B6/42

摘要： Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：US20200343175A1

公开(公告)日：2020-10-29

申请号：US16392171

申请日：2019-04-23

申请人： Intel Corporation

发明人： Zhiguo QIAN ,  Gang DUAN ,  Kemal AYGÜN ,  Jieying KONG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/66

摘要： Embodiments include package substrates and methods of forming the package substrates. A package substrate includes a first conductive layer in a first dielectric, a second dielectric over the first dielectric, and a second conductive layer in the second dielectric, where the second conductive layer includes first and second traces. The package substrate also includes a third conductive layer over the second dielectric, and a high dielectric constant (Dk) and low DK regions in the first and second dielectrics, where the high Dk region surrounds the first traces, and where the low Dk region surrounds the second traces. The high Dk region may be between the first and third conductive layers. The low Dk region may be between the first and third conductive layers. The package substrate may include a dielectric region in the first and second dielectrics, where the dielectric region separates the high Dk and low Dk regions.

公开(公告)号：US20240063100A1

公开(公告)日：2024-02-22

申请号：US17889229

申请日：2022-08-16

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Mohammad Mamunur RAHMAN ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Kemal AYGÜN ,  Cemil GEYIK

IPC分类号： H01L23/498

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/49811

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.

公开(公告)号：US20230317588A1

公开(公告)日：2023-10-05

申请号：US17707342

申请日：2022-03-29

申请人： Intel Corporation

发明人： Jiwei SUN ,  Zhiguo QIAN ,  Kemal AYGÜN

IPC分类号： H01L23/498 ,  H01L23/66

CPC分类号： H01L23/49827 ,  H01L2223/6616 ,  H01L23/66 ,  H01L23/49838

摘要： Embodiments disclosed herein include electronic packages In an embodiment, the electronic package comprises first substrate layers, and a core under the first substrate layers. In an embodiment, second substrate layers are under the core, and an interconnect is through the first substrate layers, the core, and the second substrate layers. In an embodiment, a portion of the interconnect through the second substrate layers comprises a pad, and a plurality of vias extending away from the pad.

公开(公告)号：US20210125912A1

公开(公告)日：2021-04-29

申请号：US16666202

申请日：2019-10-28

申请人： Intel Corporation

发明人： Zhiguo QIAN ,  Gang DUAN ,  Kemal AYGÜN ,  Jieying KONG ,  Brandon C. MARIN

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/66

摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

公开(公告)号：US20230091050A1

公开(公告)日：2023-03-23

申请号：US17479031

申请日：2021-09-20

申请人： Intel Corporation

发明人： Zhichao ZHANG ,  Pooya TADAYON ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Changhua LIU ,  Kemal AYGÜN

IPC分类号： G02B6/42

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed to optical interconnects and optical waveguides within a glass layer of a semiconductor package, where dies that are physically and optically coupled with the glass layer are optically coupled with each other via the optical waveguides. One or more reflectors may be used to direct the optical pathway through the glass layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220100692A1

公开(公告)日：2022-03-31

申请号：US17033593

申请日：2020-09-25

申请人： Intel Corporation

发明人： Dheeraj SUBBAREDDY ,  Ankireddy NALAMALPU ,  Anshuman THAKUR ,  MD Altaf HOSSAIN ,  Mahesh KUMASHIKAR ,  Kemal AYGÜN ,  Casey THIELEN ,  Daniel KLOWDEN ,  Sandeep B. SANE

IPC分类号： G06F13/42

摘要： Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

公开(公告)号：US20210104476A1

公开(公告)日：2021-04-08

申请号：US16596383

申请日：2019-10-08

申请人： Intel Corporation

发明人： Zhiguo QIAN ,  Cemil GEYIK ,  Jiwei SUN ,  Gang DUAN ,  Kemal AYGÜN

IPC分类号： H01L23/64 ,  H01L23/498

摘要： Embodiments include package substrates and a semiconductor package with such package substrates. A package substrate includes a first conductive layer in a first magnetic layer, and a second magnetic layer over the first magnetic layer, where the first and second magnetic layers include magnetic materials. The package substrate also includes a second conductive layer in the second magnetic layer. The second conductive layer includes a plurality of first traces fully surrounded by the first and second magnetic layers. The package substrate includes a third conductive layer over the second magnetic layer. The magnetic materials may include manganese Mn ferrite materials, Zn/Mn ferrite materials, or Ni/Zn ferrite materials. The magnetic materials include material properties with a low constant value, a magnetic tangent value, a frequency, a base filler chemistry, a filler shape, a filler orientation, a filler percentage, a loading fraction value, a permeability, an insertion loss, and a resin formulation.