Invention Application
- Patent Title: Strained Nanowire CMOS Device and Method of Forming
-
Application No.: US17656258Application Date: 2022-03-24
-
Publication No.: US20220216301A1Publication Date: 2022-07-07
- Inventor: Cheng-Yi Peng , Hung-Li Chiang , Yu-Lin Yang , Chih Chieh Yeh , Yee-Chia Yeo , Chi-Wen Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/66 ; H01L29/775 ; H01L21/8238 ; H01L21/308 ; H01L29/786 ; H01L21/306 ; H01L21/84 ; H01L27/092 ; H01L27/12 ; H01L29/423

Abstract:
Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
Public/Granted literature
- US11652141B2 Strained nanowire CMOS device and method of forming Public/Granted day:2023-05-16
Information query
IPC分类: