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公开(公告)号：US11380803B2
公开(公告)日：2022-07-05
申请号：US16837051
申请日：2020-04-01
发明人： Hou-Yu Chen , Chao-Ching Cheng , Tzu-Chiang Chen , Yu-Lin Yang , I-Sheng Chen
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L29/423
摘要： A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials. The first oxide layer is in direct contact with the isolation layer.
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公开(公告)号：US10818777B2
公开(公告)日：2020-10-27
申请号：US16837853
申请日：2020-04-01
发明人： Kuo-Cheng Chiang , Chen-Feng Hsu , Chao-Ching Cheng , Tzu-Chiang Chen , Tung Ying Lee , Wei-Sheng Yun , Yu-Lin Yang
IPC分类号： H01L29/66 , H01L29/423 , H01L29/06 , H01L29/775 , H01L29/08 , H01L29/165 , H01L29/78 , H01L21/8238 , B82Y10/00 , H01L21/02 , H01L21/3105
摘要： In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
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公开(公告)号：US20200044062A1
公开(公告)日：2020-02-06
申请号：US16600904
申请日：2019-10-14
发明人： Wei-Han Fan , Wei-Yuan Lu , Yu-Lin Yang , Chun-Hsiang Fan , Sai-Hooi Yeong
IPC分类号： H01L29/66 , H01L29/08 , H01L21/02 , H01L21/265 , H01L21/3065 , H01L29/78 , H01L21/225 , H01L21/311 , H01L21/306
摘要： A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.
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公开(公告)号：US11798989B2
公开(公告)日：2023-10-24
申请号：US17805719
申请日：2022-06-07
发明人： Cheng-Yi Peng , Hung-Li Chiang , Yu-Lin Yang , Chih Chieh Yeh , Yee-Chia Yeo , Chi-Wen Liu
IPC分类号： H01L29/06 , H01L21/82 , H01L29/66 , H01L29/775 , H01L21/8238 , H01L21/308 , H01L29/786 , H01L21/306 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/423 , H01L21/3065
CPC分类号： H01L29/0673 , H01L21/3081 , H01L21/30604 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/42392 , H01L29/66439 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/78696 , H01L21/3065
摘要： Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
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公开(公告)号：US11652141B2
公开(公告)日：2023-05-16
申请号：US17656258
申请日：2022-03-24
发明人： Cheng-Yi Peng , Hung-Li Chiang , Yu-Lin Yang , Chih Chieh Yeh , Yee-Chia Yeo , Chi-Wen Liu
IPC分类号： H01L21/82 , H01L29/06 , H01L29/66 , H01L29/775 , H01L21/8238 , H01L21/308 , H01L29/786 , H01L21/306 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/423 , H01L21/3065
CPC分类号： H01L29/0673 , H01L21/3081 , H01L21/30604 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/42392 , H01L29/66439 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/78696 , H01L21/3065
摘要： Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
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公开(公告)号：US11195763B2
公开(公告)日：2021-12-07
申请号：US16556096
申请日：2019-08-29
发明人： Hung-Li Chiang , Chao-Ching Cheng , Chih-Liang Chen , Tzu-Chiang Chen , Ta-Pen Guo , Yu-Lin Yang , I-Sheng Chen , Szu-Wei Huang
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/11 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/66
摘要： In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
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公开(公告)号：US11043577B2
公开(公告)日：2021-06-22
申请号：US16657747
申请日：2019-10-18
发明人： Chao-Ching Cheng , Yu-Lin Yang , Wei-Sheng Yun , Chen-Feng Hsu , Tzu-Chiang Chen
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/306 , H01L29/04 , H01L29/775 , H01L29/08 , B82Y10/00
摘要： A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
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公开(公告)号：US10446669B2
公开(公告)日：2019-10-15
申请号：US15964398
申请日：2018-04-27
发明人： Wei-Han Fan , Wei-Yuan Lu , Yu-Lin Yang , Chun-Hsiang Fan , Sai-Hooi Yeong
IPC分类号： H01L29/66 , H01L29/08 , H01L21/02 , H01L21/265 , H01L21/3065 , H01L29/78 , H01L21/225 , H01L21/311
摘要： A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.
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公开(公告)号：US10403550B2
公开(公告)日：2019-09-03
申请号：US15885359
申请日：2018-01-31
发明人： Hung-Li Chiang , Chao-Ching Cheng , Chih-Liang Chen , Tzu-Chiang Chen , Ta-Pen Guo , Yu-Lin Yang , I-Sheng Chen , Szu-Wei Huang
IPC分类号： H01L21/02 , H01L21/8238 , H01L27/092 , H01L27/11 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
摘要： In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
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公开(公告)号：US10355102B2
公开(公告)日：2019-07-16
申请号：US15941798
申请日：2018-03-30
发明人： Chao-Ching Cheng , Yu-Lin Yang , Wei-Sheng Yun , Chen-Feng Hsu , Tzu-Chiang Chen
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/306
摘要： A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
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