Invention Application
- Patent Title: CHIP SCALE PACKAGE
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Application No.: US17245259Application Date: 2021-04-30
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Publication No.: US20220246514A1Publication Date: 2022-08-04
- Inventor: Craig MCADAM , Jonathan TAYLOR , Douglas MACFARLANE , John KERR , James MUNGER , John PAVELKA , Steven A. ATHERTON
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee Address: GB Edinburgh
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/00
Abstract:
The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
Public/Granted literature
- US11562952B2 Chip scale package Public/Granted day:2023-01-24
Information query
IPC分类:
