Invention Application
- Patent Title: HIGH-SIDE GATE OVER-VOLTAGE STRESS TESTING
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Application No.: US17739911Application Date: 2022-05-09
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Publication No.: US20220260627A1Publication Date: 2022-08-18
- Inventor: Sigfredo E. Gonzalez Diaz , Benjamin Lee Amey , Patrick Michael Teterud , Hung Nguyen
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: G01R31/26
- IPC: G01R31/26

Abstract:
A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
Public/Granted literature
- US11624769B2 High-side gate over-voltage stress testing Public/Granted day:2023-04-11
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