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公开(公告)号：US09501074B2
公开(公告)日：2016-11-22
申请号：US14176910
申请日：2014-02-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Donghwi Kim , Patrick Michael Teterud
CPC classification number: G05F1/571
Abstract: A circuit includes a comparator that monitors a transient with respect to a predetermined threshold at the output of a voltage regulator and generates a compensation signal if the transient exceeds the predetermined threshold. A dynamic current pull-down block is triggered from the compensation signal of the comparator and operative with an output stage of the voltage regulator to mitigate the transient at the output of the voltage regulator by concurrently activating a plurality of current pull-down switches during the transient and sequentially deactivating each current pull-down switch of the plurality of current pull-down switches after its predetermined deactivation delay for each current pull-down switch.
Abstract translation: 一个电路包括一个比较器，用于在电压调节器的输出处监测相对于预定阈值的瞬变，并且如果瞬变超过预定阈值则产生补偿信号。 动态电流下拉块从比较器的补偿信号触发，并与电压调节器的输出级一起工作，以通过在期间同时激活多个电流下拉开关来减轻电压调节器输出端的瞬变 在每个电流下拉开关的预定去激活延迟之后，暂时并且顺序地去激活多个电流下拉开关中的每个电流下拉开关。
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公开(公告)号：US20220260627A1
公开(公告)日：2022-08-18
申请号：US17739911
申请日：2022-05-09
Applicant: Texas Instruments Incorporated
Inventor： Sigfredo E. Gonzalez Diaz , Benjamin Lee Amey , Patrick Michael Teterud , Hung Nguyen
IPC: G01R31/26
Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
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公开(公告)号：US11353494B2
公开(公告)日：2022-06-07
申请号：US16792671
申请日：2020-02-17
Applicant: Texas Instruments Incorporated
Inventor： Sigfredo E. Gonzalez Diaz , Benjamin Lee Amey , Patrick Michael Teterud , Hung Nguyen
IPC: G01R31/26
Abstract: A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.
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公开(公告)号：US11624769B2
公开(公告)日：2023-04-11
申请号：US17739911
申请日：2022-05-09
Applicant: Texas Instruments Incorporated
Inventor： Sigfredo E. Gonzalez Diaz , Benjamin Lee Amey , Patrick Michael Teterud , Hung Nguyen
IPC: G01R31/26
Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
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Patent Agency Ranking
公开(公告)号：US20180180661A1
公开(公告)日：2018-06-28
申请号：US15389443
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Sigfredo E. Gonzalez Diaz , Benjamin Lee Amey , Patrick Michael Teterud , Hung Nguyen
IPC: G01R31/26
CPC classification number: G01R31/2623
Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
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公开(公告)号：US09411353B2
公开(公告)日：2016-08-09
申请号：US14194103
申请日：2014-02-28
Applicant: Texas Instruments Incorporated
Inventor： Seenu Gopalraju , Patrick Michael Teterud , Shanmuganand Chellamuthu
Abstract: In response to a first reference voltage, a regulator regulates an output voltage of a line, so that the output voltage is approximately equal to a target voltage. In response to the output voltage rising above a second reference voltage, pull down circuitry draws current from the line. In response to the output voltage falling below the second reference voltage by at least a predetermined amount, the pull down circuitry ceases to draw current from the line. The first and second reference voltages are based upon a same band gap reference as one another.
Abstract translation: 响应于第一参考电压，调节器调节线路的输出电压，使得输出电压近似等于目标电压。 响应于输出电压上升到高于第二参考电压，下拉电路从线路中吸取电流。 响应于输出电压低于第二参考电压至少预定量，下拉电路停止从线路中吸取电流。 第一和第二参考电压基于彼此相同的带隙基准。
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公开(公告)号：US20200182925A1
公开(公告)日：2020-06-11
申请号：US16792671
申请日：2020-02-17
Applicant: Texas Instruments Incorporated
Inventor： Sigfredo E. Gonzalez Diaz , Benjamin Lee Amey , Patrick Michael Teterud , Hung Nguyen
IPC: G01R31/26
Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
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公开(公告)号：US20150248137A1
公开(公告)日：2015-09-03
申请号：US14194103
申请日：2014-02-28
Applicant: Texas Instruments Incorporated
Inventor： Seenu Gopalraju , Patrick Michael Teterud , Shanmuganand Chellamuthu
Abstract: In response to a first reference voltage, a regulator regulates an output voltage of a line, so that the output voltage is approximately equal to a target voltage. In response to the output voltage rising above a second reference voltage, pull down circuitry draws current from the line. In response to the output voltage falling below the second reference voltage by at least a predetermined amount, the pull down circuitry ceases to draw current from the line. The first and second reference voltages are based upon a same band gap reference as one another.
Abstract translation: 响应于第一参考电压，调节器调节线路的输出电压，使得输出电压近似等于目标电压。 响应于输出电压上升到高于第二参考电压，下拉电路从线路中吸取电流。 响应于输出电压低于第二参考电压至少预定量，下拉电路停止从线路中吸取电流。 第一和第二参考电压基于彼此相同的带隙基准。
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公开(公告)号：US20150229124A1
公开(公告)日：2015-08-13
申请号：US14176910
申请日：2014-02-10
Applicant: Texas Instruments Incorporated
Inventor： Donghwi Kim , Patrick Michael Teterud
CPC classification number: G05F1/571
Abstract: A circuit includes a comparator that monitors a transient with respect to a predetermined threshold at the output of a voltage regulator and generates a compensation signal if the transient exceeds the predetermined threshold. A dynamic current pull-down block is triggered from the compensation signal of the comparator and operative with an output stage of the voltage regulator to mitigate the transient at the output of the voltage regulator by concurrently activating a plurality of current pull-down switches during the transient and sequentially deactivating each current pull-down switch of the plurality of current pull-down switches after its predetermined deactivation delay for each current pull-down switch.
Abstract translation: 一个电路包括一个比较器，用于在电压调节器的输出处监测相对于预定阈值的瞬变，并且如果瞬变超过预定阈值则产生补偿信号。 动态电流下拉块从比较器的补偿信号触发，并与电压调节器的输出级一起工作，以通过在期间同时激活多个电流下拉开关来减轻电压调节器输出端的瞬变 在每个电流下拉开关的预定去激活延迟之后，暂时并且顺序地去激活多个电流下拉开关中的每个电流下拉开关。
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