Invention Application
- Patent Title: VERTICAL TRANSISTORS WITH GATE CONNECTION GRID
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Application No.: US17194846Application Date: 2021-03-08
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Publication No.: US20220285248A1Publication Date: 2022-09-08
- Inventor: Thomas NEYER , Herbert DE VLEESCHOUWER , Fredrik ALLERSTAM
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Main IPC: H01L23/482
- IPC: H01L23/482 ; H01L29/16 ; H01L29/10 ; H01L29/739 ; H01L29/78 ; H01L21/768 ; H01L29/66

Abstract:
In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric.
Public/Granted literature
- US11652027B2 Vertical transistors with gate connection grid Public/Granted day:2023-05-16
Information query
IPC分类: