Invention Application
- Patent Title: REDUCING PROGRAM VERIFIES FOR MULTI-LEVEL NAND CELLS
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Application No.: US17873716Application Date: 2022-07-26
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Publication No.: US20220359025A1Publication Date: 2022-11-10
- Inventor: Jeffrey S. McNeil , Jason Lee Nevill , Tommaso Vali
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/04 ; G11C11/56 ; G06F3/06 ; G11C16/10

Abstract:
Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.
Public/Granted literature
- US11887680B2 Reducing program verifies for multi-level NAND cells Public/Granted day:2024-01-30
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