Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.