公开(公告)号：US20200303381A1

公开(公告)日：2020-09-24

申请号：US16357221

申请日：2019-03-18

Applicant: Intel Corporation

Inventor： Elijah KARPOV ,  Brian DOYLE ,  Abhishek SHARMA ,  Prashant MAJHI ,  Pulkit JAIN

IPC: H01L27/11 ,  H01L49/02 ,  H05K1/18

Abstract: Embodiments herein describe techniques for a semiconductor device including a SRAM device having multiple SRAM memory cells, and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is to supply power to the multiple SRAM memory cells of the SRAM device in parallel for a period of time. Other embodiments may be described and/or claimed.

公开(公告)号：US20200227477A1

公开(公告)日：2020-07-16

申请号：US16631156

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20190229264A1

公开(公告)日：2019-07-25

申请号：US16320010

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Roza KOTLYAR ,  Prashant MAJHI ,  Jeffery D. BIELEFELD

IPC: H01L45/00

Abstract: Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.

公开(公告)号：US20220199839A1

公开(公告)日：2022-06-23

申请号：US17133599

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arnab SEN GUPTA ,  Urusa ALAAN ,  Justin WEBER ,  Charles C. KUO ,  Yu-Jin CHEN ,  Kaan OGUZ ,  Matthew V. METZ ,  Abhishek A. SHARMA ,  Prashant MAJHI ,  Brian S. DOYLE ,  Van H. LE

IPC: H01L29/872 ,  H01L27/07 ,  H01L29/47 ,  H01L29/22

Abstract: Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

公开(公告)号：US20220109025A1

公开(公告)日：2022-04-07

申请号：US17552546

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20200212105A1

公开(公告)日：2020-07-02

申请号：US16634109

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Abhishek A. SHARMA ,  Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Brian S. DOYLE

IPC: H01L27/24 ,  H01L27/22

Abstract: Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includes a first electrode material layer, a selector material layer on the first electrode material layer, and a second electrode material layer on the selector material layer, the second electrode material layer different in composition than the first electrode material layer. A bipolar memory element is above the word line, the bipolar memory element on the asymmetric selector element. A bit line is above the word line.

公开(公告)号：US20220359441A1

公开(公告)日：2022-11-10

申请号：US17314979

申请日：2021-05-07

Applicant: Intel Corporation

Inventor： Khaled HASNAT ,  Prashant MAJHI ,  Owen JUNGROTH ,  Richard FASTOW ,  Krishna K. PARAT

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.

公开(公告)号：US20220199801A1

公开(公告)日：2022-06-23

申请号：US17132996

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Brian S. DOYLE ,  Urusa ALAAN ,  Van H. LE ,  Elijah V. KARPOV ,  Kaan OGUZ ,  Arnab SEN GUPTA

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/683 ,  H01L29/78

Abstract: Embodiments disclosed herein include a semiconductor devices with back end of line (BEOL) transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a BEOL stack over the semiconductor substrate. In an embodiment, a field effect transistor (FET) is embedded in the BEOL stack. In an embodiment, the FET comprises a channel, a gate dielectric over the channel, where the gate dielectric is single crystalline, a gate electrode over the gate dielectric, and a source electrode and a drain electrode passing through the gate dielectric to contact the channel.

公开(公告)号：US20220199609A1

公开(公告)日：2022-06-23

申请号：US17133595

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Urusa ALAAN ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Benjamin ORR ,  Nicholas THOMSON ,  Ayan KAR ,  Arnab SEN GUPTA ,  Kaan OGUZ ,  Brian S. DOYLE ,  Prashant MAJHI ,  Van H. LE ,  Elijah V. KARPOV

IPC: H01L27/02 ,  H02H9/04

Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

公开(公告)号：US20220181335A1

公开(公告)日：2022-06-09

申请号：US17673670

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: H01L27/1159 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.