公开(公告)号：US20210117270A1

公开(公告)日：2021-04-22

申请号：US17133995

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Krishna K. PARAT ,  Ravi H. MOTWANI ,  Rohit S. SHENOY ,  Ali KHAKIFIROOZ

IPC: G06F11/10 ,  G11C16/26 ,  G11C11/56

Abstract: Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.

公开(公告)号：US20180122487A1

公开(公告)日：2018-05-03

申请号：US15715980

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Shantanu R. RAJWADE ,  Pranav KALAVADE ,  Neal R. MIELKE ,  Krishna K. PARAT ,  Shyam Sunder RAGHUNATHAN

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US20220359441A1

公开(公告)日：2022-11-10

申请号：US17314979

申请日：2021-05-07

Applicant: Intel Corporation

Inventor： Khaled HASNAT ,  Prashant MAJHI ,  Owen JUNGROTH ,  Richard FASTOW ,  Krishna K. PARAT

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.

公开(公告)号：US20200342946A1

公开(公告)日：2020-10-29

申请号：US16396478

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Han ZHAO ,  Richard FASTOW ,  Krishna K. PARAT ,  Arun THATHACHARY ,  Narayanan RAMANAN

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08

Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.

公开(公告)号：US20190287627A1

公开(公告)日：2019-09-19

申请号：US16412269

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Krishna K. PARAT ,  Pranav KALAVADE ,  Koichi Kawai ,  Akira Goda

IPC: G11C16/16 ,  G11C16/34 ,  G11C8/12 ,  G11C16/04

Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify