Invention Application
- Patent Title: STAGGERED READ RECOVERY FOR IMPROVED READ WINDOW BUDGET IN A THREE DIMENSIONAL (3D) NAND MEMORY ARRAY
-
Application No.: US17322724Application Date: 2021-05-17
-
Publication No.: US20220366962A1Publication Date: 2022-11-17
- Inventor: Rifat FERDOUS , Sung-Taeg KANG , Rohit S. SHENOY , Ali KHAKIFIROOZ , Dipanjan BASU
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G11C11/408
- IPC: G11C11/408 ; G11C11/4074 ; G11C11/409 ; G11C7/04

Abstract:
After reading a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a read voltage for reading operations and then transition a selected wordline of the multiple wordlines from the read voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the read voltage to ground after a delay.
Information query
IPC分类: