Invention Application
- Patent Title: REDUCTION OF GATE-DRAIN CAPACITANCE
-
Application No.: US17874478Application Date: 2022-07-27
-
Publication No.: US20220367463A1Publication Date: 2022-11-17
- Inventor: Jung-Hung Chang , Lo-Heng Chang , Zhi-Chang Lin , Shih-Cheng Chen , Kuo-Cheng Chiang , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/02 ; H01L21/8238 ; H01L29/08 ; H01L29/78 ; H01L29/66 ; H01L29/10

Abstract:
A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
Information query
IPC分类: