Invention Application
- Patent Title: Reducing Parasitic Capacitance in Semiconductor Devices
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Application No.: US17868678Application Date: 2022-07-19
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Publication No.: US20220376044A1Publication Date: 2022-11-24
- Inventor: Chia-Ta Yu , Hsiao-Chiu Hsu , Feng-Cheng Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L27/088 ; H01L29/66 ; H01L21/762 ; H01L29/78

Abstract:
A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.
Public/Granted literature
- US11881507B2 Reducing parasitic capacitance in semiconductor devices Public/Granted day:2024-01-23
Information query
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