Reducing parasitic capacitance in semiconductor devices

    公开(公告)号:US11437469B2

    公开(公告)日:2022-09-06

    申请号:US17198774

    申请日:2021-03-11

    Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

    Reducing Parasitic Capacitance in Semiconductor Devices

    公开(公告)号:US20220376044A1

    公开(公告)日:2022-11-24

    申请号:US17868678

    申请日:2022-07-19

    Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

    Reducing Parasitic Capacitance in Semiconductor Devices

    公开(公告)号:US20210376072A1

    公开(公告)日:2021-12-02

    申请号:US17198774

    申请日:2021-03-11

    Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

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