Invention Application
- Patent Title: INTERCONNECT STRUCTURE AND METHOD
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Application No.: US17883986Application Date: 2022-08-09
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Publication No.: US20220384334A1Publication Date: 2022-12-01
- Inventor: Bo-Jiun Lin , Yu Chao Lin , Tung Ying Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L29/66 ; H01L23/532

Abstract:
An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.
Public/Granted literature
- US12094771B2 Interconnect structure and method Public/Granted day:2024-09-17
Information query
IPC分类: