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    Semiconductor Memory Devices and Methods of Manufacture
    5.
    发明申请
    Semiconductor Memory Devices and Methods of Manufacture 有权

    公开(公告)号：US20220336742A1

    公开(公告)日：2022-10-20

    申请号：US17383726

    申请日：2021-07-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Kai-Tai Chang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.

    FinFETs with low source/drain contact resistance
    6.
    发明授权
    FinFETs with low source/drain contact resistance 有权

    公开(公告)号：US11271095B2

    公开(公告)日：2022-03-08

    申请号：US16910662

    申请日：2020-06-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Lien Huang ,  Tung Ying Lee

    IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45

    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

    Semiconductor device and manufacturing method thereof
    8.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11183584B2

    公开(公告)日：2021-11-23

    申请号：US16746127

    申请日：2020-01-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Hsuan Hsiao ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Jin Cai

    IPC: H01L29/786 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306

    Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate. A thickness of the first semiconductor layers as formed increases in each first semiconductor layer spaced further apart from the substrate in the first direction. The stacked structure is patterned into a fin structure extending along a second direction substantially perpendicular to the first direction. A portion of the first semiconductor layers between adjacent second semiconductor layers is removed, and a gate structure is formed extending in a third direction over a first portion of the first semiconductor layers so that the gate structure wraps around the first semiconductor layers. The third direction is substantially perpendicular to both the first direction and the second direction. Each of the first semiconductor layers at the first portion of the first semiconductor layers have a substantially same thickness.

    PHASE-CHANGE MEMORY DEVICE AND METHOD
    9.
    发明申请
    PHASE-CHANGE MEMORY DEVICE AND METHOD 有权

    公开(公告)号：US20210336138A1

    公开(公告)日：2021-10-28

    申请号：US16992210

    申请日：2020-08-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tung Ying Lee ,  Yu Chao Lin ,  Shao-Ming Yu

    IPC: H01L45/00

    Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

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