Invention Application
- Patent Title: GATE ALL AROUND TRANSISTOR WITH DUAL INNER SPACERS
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Application No.: US17370833Application Date: 2021-07-08
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Publication No.: US20230012216A1Publication Date: 2023-01-12
- Inventor: Zhi-Chang LIN , Kuan-Ting PAN , Shih-Cheng CHEN , Jung-Hung CHANG , Lo-Heng CHANG , Chien-Ning YAO , Kuo-Cheng CHIANG
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/06 ; H01L29/786 ; H01L29/66 ; H01L29/40
Abstract:
A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
Public/Granted literature
- US11916122B2 Gate all around transistor with dual inner spacers Public/Granted day:2024-02-27
Information query
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