公开(公告)号：US20230420513A1

公开(公告)日：2023-12-28

申请号：US17850811

申请日：2022-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jung-Hung CHANG ,  Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Tsung-Han CHUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/0673 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/0649 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66439

摘要： An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.

公开(公告)号：US20230134741A1

公开(公告)日：2023-05-04

申请号：US17736036

申请日：2022-05-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Xuan HUANG ,  Hou-Yu CHEN ,  Jin CAI ,  Zhi-Chang LIN ,  Chih-Hao WANG

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L21/22 ,  H01L29/66

摘要： A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

公开(公告)号：US20220336613A1

公开(公告)日：2022-10-20

申请号：US17564125

申请日：2021-12-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Ju LEE ,  Zhi-Chang LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

摘要： A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.

公开(公告)号：US20210320210A1

公开(公告)日：2021-10-14

申请号：US16847204

申请日：2020-04-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

摘要： A semiconductor device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer.

公开(公告)号：US20210296468A1

公开(公告)日：2021-09-23

申请号：US17339795

申请日：2021-06-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zhi-Chang LIN ,  Wei-Hao WU ,  Jia-Ni YU

IPC分类号： H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

摘要： A method includes forming an active fin using a hard mask as an etching mask, wherein the active fin comprises a source region, a drain region, and a channel region, the hard mask remains over the active fin after etching the semiconductive substrate, and the hard mask has a first portion vertically overlapping the source region of the active fin, a second portion vertically overlapping the channel region of the active fin, and a third portion vertically overlapping the drain region of the active fin. A sacrificial gate is formed over the second portion of the hard mask and the channel region of the active fin. The first and third portions of the hard mask are etched. After etching the first and third portions of the hard mask, a gate spacer is formed extending along sidewalls of the sacrificial gate, and the sacrificial gate is replaced with a replacement gate.

公开(公告)号：US20230215950A1

公开(公告)日：2023-07-06

申请号：US18120879

申请日：2023-03-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/78609 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

公开(公告)号：US20230012216A1

公开(公告)日：2023-01-12

申请号：US17370833

申请日：2021-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Zhi-Chang LIN ,  Kuan-Ting PAN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO ,  Kuo-Cheng CHIANG

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40

摘要： A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

公开(公告)号：US20220093785A1

公开(公告)日：2022-03-24

申请号：US17025903

申请日：2020-09-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Cheng CHEN ,  Zhi-Chang LIN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

摘要： Embodiments of the present disclosure relate to an un-doped or low-doped epitaxial layer formed below the source/drain features. The un-doped or low-doped epitaxial layer protects the source/drain features from damage during replacement gate processes, and also prevent leakage currents in the mesa device. A semiconductor device is disclosed. The semiconductor device includes an epitaxial feature having a dopant of a first concentration, and a source/drain feature in contact with the epitaxial feature. The source/drain feature comprises the dopant of a second concentration, and the second concentration is higher than the first concentration.

公开(公告)号：US20200328208A1

公开(公告)日：2020-10-15

申请号：US16910574

申请日：2020-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Chih-Hao WANG ,  Kuan-Ting PAN ,  Zhi-Chang LIN

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

摘要： A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure also includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the first dummy fin structure, and a top surface of the capping layer is higher than a top surface of the first stacked structure and a top surface of the second stacked structure.

公开(公告)号：US20200243665A1

公开(公告)日：2020-07-30

申请号：US16260483

申请日：2019-01-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuo-Cheng CHING ,  Zhi-Chang LIN ,  Kuan-Ting PAN ,  Chih-Hao WANG ,  Shi-Ning JU

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/088

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.