公开(公告)号：US20240312993A1

公开(公告)日：2024-09-19

申请号：US18354515

申请日：2023-07-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Wei HSU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit includes an NMOS gate all around (GAA) transistor and a PMOS GAA transistor. A single gate metal is utilized for both transistors. An effective work function is imparted to the NMOS transistor by including a first layer of the gate metal around the channels, a semiconductor layer around the first layer of the gate metal, and a gate fill layer of the gate metal on the semiconductor layer. The PMOS transistor, the gate fill layer of the gate metal is on the gate dielectric without an intervening semiconductor layer.

公开(公告)号：US20240282838A1

公开(公告)日：2024-08-22

申请号：US18343680

申请日：2023-06-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jung-Hung CHANG ,  Tsung-Han CHUANG ,  Fu-Cheng CHANG ,  Shih-Cheng CHEN ,  Chia-Cheng TSAI ,  Kuo-Cheng CHIANG

IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/823807

摘要： A device includes: a stack of nanostructures; a gate structure that wraps around the nanostructures; an isolation region between the stack of nanostructures and another stack of nanostructures adjacent thereto along a first direction; a source/drain region that abuts at least one of the nanostructures; and a spacer layer that is on sidewalls of the gate structure and on sidewalls of the source/drain region, the spacer layer covering an area between the source/drain region and a neighboring source/drain region of another transistor along the first direction.

公开(公告)号：US20240222508A1

公开(公告)日：2024-07-04

申请号：US18438758

申请日：2024-02-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shi Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L21/76224 ,  H01L21/823418

摘要： A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.

公开(公告)号：US20230420513A1

公开(公告)日：2023-12-28

申请号：US17850811

申请日：2022-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jung-Hung CHANG ,  Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Tsung-Han CHUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/0673 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/0649 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66439

摘要： An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.

公开(公告)号：US20230142902A1

公开(公告)日：2023-05-11

申请号：US17750239

申请日：2022-05-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shi Ning JU ,  Wen-Ting LAN ,  I-Han HUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L23/00

CPC分类号： H01L24/80 ,  H01L24/08 ,  H01L24/98 ,  H01L2924/35121 ,  H01L2224/08225 ,  H01L2224/80006 ,  H01L2224/80896

摘要： A method of manufacturing a semiconductor device structure includes bonding a device substrate to a first de-bond layer. The first de-bond layer is disposed on a first carrier substrate, and the device substrate has a first side facing the first carrier substrate and a second side opposite from the first side. The device substrate has a first width. A front-end-of-line (FEOL) process and a back-end-of-line (BEOL) process are performed on the device substrate. A second carrier substrate having a second de-bond layer is bonded on the second side of the device substrate. The first carrier substrate is removed by removing the first de-bond layer. A width of the device substrate remains the first width after removing the first carrier substrate.

公开(公告)号：US20230023916A1

公开(公告)日：2023-01-26

申请号：US17581787

申请日：2022-01-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Chu-Yuan HSU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

摘要： An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

公开(公告)号：US20230014998A1

公开(公告)日：2023-01-19

申请号：US17379936

申请日：2021-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG ,  Guan-Lin CHEN ,  Kuan-Ting PAN

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

摘要： A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

公开(公告)号：US20230010502A1

公开(公告)日：2023-01-12

申请号：US17370843

申请日：2021-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

摘要： A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

公开(公告)号：US20220344333A1

公开(公告)日：2022-10-27

申请号：US17476418

申请日：2021-09-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Ruei Jhan ,  Kuan-Ting Pan ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

摘要： A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, an isolation feature embedded in the substrate and laterally between the first and second semiconductor channels, a first liner layer laterally surrounding the isolation feature between the isolation feature and the first semiconductor channel, and a second liner layer laterally surrounding the first liner layer between the first liner layer and the first semiconductor channel.

公开(公告)号：US20220115498A1

公开(公告)日：2022-04-14

申请号：US17070717

申请日：2020-10-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.