Invention Publication
- Patent Title: LOW RESISTIVITY DRAM BURIED WORD LINE STACK
-
Application No.: US18149226Application Date: 2023-01-03
-
Publication No.: US20230141748A1Publication Date: 2023-05-11
- Inventor: Yixiong Yang , Jacqueline S. Wrench , Yong Yang , Srinivas Gandikota , Annamalai Lakshmanan , Joung Joo Lee , Feihu Wang , Seshadri Ganguli
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: H10B12/00
- IPC: H10B12/00 ; H01L21/285 ; C23C16/455 ; H01L21/02
Abstract:
Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.
Public/Granted literature
- US12022650B2 Low resistivity DRAM buried word line stack Public/Granted day:2024-06-25
Information query
