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    INTEGRATED DIPOLE REGION FOR TRANSISTOR
    2.
    发明申请
    INTEGRATED DIPOLE REGION FOR TRANSISTOR 有权

    公开(公告)号：US20250006499A1

    公开(公告)日：2025-01-02

    申请号：US18823999

    申请日：2024-09-04

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Steven C.H. Hung ,  Tianyi Huang ,  Seshadri Ganguli

    IPC: H01L21/28 ,  H01L21/324 ,  H01L21/8238

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

    DIPOLE FORMATION PROCESSES
    3.
    发明公开
    DIPOLE FORMATION PROCESSES 审中-公开

    公开(公告)号：US20240222195A1

    公开(公告)日：2024-07-04

    申请号：US18108719

    申请日：2023-02-13

    Applicant: Applied Materials, Inc.

    Inventor： Tianyi Huang ,  Srinivas Gandikota ,  Yixiong Yang ,  Tengzhou Ma ,  Steven C.H. Hung ,  Hsin-Jung Yu ,  Geetika Bajaj

    IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L21/823462 ,  H01L29/42392 ,  H01L29/78696

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 Å, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.

    CONFORMAL MOLYBDENUM DEPOSITION
    6.
    发明公开
    CONFORMAL MOLYBDENUM DEPOSITION 审中-公开

    公开(公告)号：US20240060175A1

    公开(公告)日：2024-02-22

    申请号：US17891753

    申请日：2022-08-19

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Yong Yang ,  Tuerxun Ailihumaer ,  Yogesh Sharma ,  Kunal Bhatnagar ,  Mohith Verghese

    IPC: C23C16/06 ,  H01L21/285 ,  C23C16/455

    CPC classification number: C23C16/06 ,  H01L21/28556 ,  C23C16/45553

    Abstract: Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include forming a nucleation layer directly on a dielectric layer on a substrate surface by exposing the substrate surface to a molybdenum-containing precursor and a nucleation reactant, and conformally depositing a molybdenum film on the nucleation layer. Another aspect of the disclosure pertains to a method that is part of a gap fill process, comprising forming a nucleation layer directly on a dielectric region within one or more high aspect ratio gap features, including vertical gap features and/or horizontal gap features, and conformally depositing a molybdenum film on the nucleation layer to fill the feature.

    CONFORMAL MOLYBDENUM DEPOSITION
    7.
    发明公开
    CONFORMAL MOLYBDENUM DEPOSITION 审中-公开

    公开(公告)号：US20240026529A1

    公开(公告)日：2024-01-25

    申请号：US18222589

    申请日：2023-07-17

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Tuerxun Ailihumaer ,  Yixiong Yang ,  Seshadri Ganguli ,  Yogesh Sharma

    IPC: C23C16/08 ,  C23C16/02 ,  C23C16/04

    CPC classification number: C23C16/08 ,  C23C16/0272 ,  C23C16/045

    Abstract: Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include converting an amorphous silicon layer to a metal layer by thermally soaking the amorphous silicon layer comprising silicon atoms in the presence of a metal compound selected from the group consisting of a molybdenum compound and a tungsten compound until at least a portion of the silicon atoms in the amorphous silicon layer are replaced by metal atoms selected from the group consisting of molybdenum atoms and tungsten atoms. The methods include conformally depositing a molybdenum film on the metal layer.

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