A system includes a bridge circuit configured for low latency communication among integrated circuits (ICs). The bridge circuit includes a plurality of transceiver circuits. Each transceiver circuit is coupled to a corresponding parallel channel in the IC. Each transceiver circuit is configured to send and receive data over the corresponding parallel channel. Each transceiver circuit includes a transmit channel configured to packetized data received from the corresponding parallel channel for transmission over a serial link to a second IC. Each transceiver circuit includes a receive channel configured to depacketize data received from the serial link from the second IC. The serial link is asynchronous to each of parallel channel coupled to the first bridge circuit.