公开(公告)号：US12099790B1

公开(公告)日：2024-09-24

申请号：US17204431

申请日：2021-03-17

Applicant: Xilinx, Inc.

Inventor： Raghukul B. Dikshit ,  Tauheed Ashraf ,  Michael Chyziak

IPC: G06F30/331 ,  H04J3/06

CPC classification number: G06F30/331 ,  H04J3/06

Abstract: An emulation system can include a first integrated circuit (IC) including first circuitry and a first transceiver. The first circuitry is configured to emulate a first partition of a circuit design. The first circuitry is clocked by an emulation clock and the first transceiver is clocked by a transceiver clock asynchronous with the emulation clock. The transceiver clock has a higher frequency than the emulation clock. The emulation system can include a second IC configured to emulate a second partition of the circuit design. The second IC includes a second transceiver. The first transceiver is configured to generate multiplexed emulation data by multiplexing a plurality of nets that cross from the first partition to the second partition of the circuit design. The first transceiver is configured to send the multiplexed emulation data over a serial communication channel to the second transceiver. The multiplexed emulation data includes a clock signal of the first transceiver embedded therein.

公开(公告)号：US11329665B1

公开(公告)日：2022-05-10

申请号：US16710522

申请日：2019-12-11

Applicant: Xilinx, Inc.

Inventor： Mohammad Saifee Dohadwala ,  Raghukul B. Dikshit

IPC: H03M1/00 ,  H03M7/30 ,  H04N19/60

Abstract: Disclosed approaches for performing a Burrows-Wheeler transform (BWT) of a sequence of data elements, S, include determining sets of less-than values and sets of equal-to values for the data elements. Index values are determined for the data elements based on the sets of less-than values. Each index value indicates a count of data elements of S that a data element is lexicographically greater than. Rank values are determined for the data elements of S based on the sets of less-than values and the sets of equal-to values. Each rank value indicates for the data element an order of the data element in the BWT relative to other ones of the data elements of equal value. Positions in the BWT of S for the data elements are selected based on the index values and rank values, and the data elements are output in the order indicated by the respective positions in the BWT.

公开(公告)号：US11748289B2

公开(公告)日：2023-09-05

申请号：US17455125

申请日：2021-11-16

Applicant: Xilinx, Inc.

Inventor： Michael Chyziak ,  Raghukul B. Dikshit

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282

Abstract: A system includes a bridge circuit configured for low latency communication among integrated circuits (ICs). The bridge circuit includes a plurality of transceiver circuits. Each transceiver circuit is coupled to a corresponding parallel channel in the IC. Each transceiver circuit is configured to send and receive data over the corresponding parallel channel. Each transceiver circuit includes a transmit channel configured to packetized data received from the corresponding parallel channel for transmission over a serial link to a second IC. Each transceiver circuit includes a receive channel configured to depacketize data received from the serial link from the second IC. The serial link is asynchronous to each of parallel channel coupled to the first bridge circuit.

公开(公告)号：US20230153260A1

公开(公告)日：2023-05-18

申请号：US17455125

申请日：2021-11-16

Applicant: Xilinx, Inc.

Inventor： Michael Chyziak ,  Raghukul B. Dikshit

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282

Abstract: A system includes a bridge circuit configured for low latency communication among integrated circuits (ICs). The bridge circuit includes a plurality of transceiver circuits. Each transceiver circuit is coupled to a corresponding parallel channel in the IC. Each transceiver circuit is configured to send and receive data over the corresponding parallel channel. Each transceiver circuit includes a transmit channel configured to packetized data received from the corresponding parallel channel for transmission over a serial link to a second IC. Each transceiver circuit includes a receive channel configured to depacketize data received from the serial link from the second IC. The serial link is asynchronous to each of parallel channel coupled to the first bridge circuit.