Invention Publication
- Patent Title: ENCODER, ENCODING METHOD, DECODER, AND DECODING METHOD
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Application No.: US18148990Application Date: 2022-12-30
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Publication No.: US20230156191A1Publication Date: 2023-05-18
- Inventor: Sughosh Pavan SHASHIDHAR , Hai Wei SUN , Chong Soon LIM , Ru Ling LIAO , Han Boon TEO , Jing Ya LI , Takahiro NISHI , Kiyofumi ABE , Ryuichi KANOH , Tadamasa TOMA
- Applicant: Panasonic Intellectual Property Corporation of America
- Applicant Address: US CA Torrance
- Assignee: Panasonic Intellectual Property Corporation of America
- Current Assignee: Panasonic Intellectual Property Corporation of America
- Current Assignee Address: US CA Torrance
- Main IPC: H04N19/119
- IPC: H04N19/119 ; H04N19/60 ; H04N19/184 ; H04N19/176

Abstract:
An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; splits the block into a plurality of sub blocks in a second direction parallel to the second shorter side of the block when the ternary split process is not allowed; and encodes the plurality of sub blocks.
Public/Granted literature
- US11882283B2 Encoder, encoding method, decoder, and decoding method Public/Granted day:2024-01-23
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