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公开(公告)号：US20240031570A1
公开(公告)日：2024-01-25
申请号：US18365762
申请日：2023-08-04
发明人： Chong Soon LIM , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Ru Ling LIAO , Takahiro NISHI , Tadamasa TOMA
IPC分类号： H04N19/119 , H04N19/60 , H04N19/50 , H04N19/176
CPC分类号： H04N19/119 , H04N19/60 , H04N19/50 , H04N19/176
摘要： An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.
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公开(公告)号：US20230421762A1
公开(公告)日：2023-12-28
申请号：US18462232
申请日：2023-09-06
发明人： Sughosh Pavan SHASHIDHAR , Hai Wei SUN , Chong Soon LIM , Ru Ling LIAO , Han Boon TEO , Jing Ya LI , Takahiro NISHI , Kiyofumi ABE , Ryuichi KANOH , Tadamasa TOMA
IPC分类号： H04N19/119 , H04N19/176 , H04N19/423 , H04N19/63
CPC分类号： H04N19/119 , H04N19/176 , H04N19/423 , H04N19/63
摘要： An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: splits the current block into a first sub block, a second sub block, and a third sub block in a first direction, the second sub block being located between the first sub block and the third sub block; prohibits splitting the second sub block into two partitions in the first direction; and encodes the first sub block, the second sub block, and the third sub block.
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公开(公告)号：US20230412832A1
公开(公告)日：2023-12-21
申请号：US18241479
申请日：2023-09-01
发明人： Jing Ya LI , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Han Boon TEO , Kiyofumi ABE , Tadamasa TOMA , Takahiro NISHI
IPC分类号： H04N19/513 , H04N19/433
CPC分类号： H04N19/513 , H04N19/433
摘要： An encoder includes: circuitry; and memory coupled to the circuitry. In operation, the circuitry: derives a base motion vector to be used in predicting a current block to be encoded; derives a first motion vector different from the base motion vector; derives a motion vector difference based on a difference between the base motion vector and the first motion vector; determines whether the motion vector difference is greater than a threshold; modifies the first motion vector when the motion vector difference is determined to be greater than the threshold, and does not modify the first motion vector when the motion vector difference is determined not to be greater than the threshold; and encodes the current block using the first motion vector modified or the first motion vector not modified.
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4.发明公开公开(公告)号：US20230396776A1
公开(公告)日：2023-12-07
申请号：US18234504
申请日：2023-08-16
发明人： Jing Ya LI , Ru Ling LIAO , Chong Soon LIM , Han Boon TEO , Hai Wei SUN , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC分类号： H04N19/159 , H04N19/117 , H04N19/182
CPC分类号： H04N19/159 , H04N19/117 , H04N19/182
摘要： An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of gradient values in first and second ranges; derives, as a first parameter, a total sum of absolute values of sums of gradient values derived respectively for pairs of relative pixel positions; derives a pixel difference value between pixel values in the first and second ranges; inverts or maintains a plus or minus sign of the pixel difference value, according to a plus or minus sign of the sum of the gradient values indicating the sum of the gradient values in the first and second ranges; derives, as a second parameter, a total sum of pixel difference values each having the plus or minus sign inverted or maintained, the pixel difference values derived respectively for the relative pixel positions; and generates a prediction image using the first and second parameters.
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公开(公告)号：US20230096489A1
公开(公告)日：2023-03-30
申请号：US17944866
申请日：2022-09-14
发明人： Ru Ling LIAO , Chong Soon LIM , Hai Wei SUN , Han Boon TEO , Jing Ya LI , Sughosh Pavan SHASHIDHAR , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC分类号： H04N19/105 , H04N19/159 , H04N19/176
摘要： An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.
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公开(公告)号：US20230042791A1
公开(公告)日：2023-02-09
申请号：US17945629
申请日：2022-09-15
发明人： Ru Ling LIAO , Chong Soon LIM , Hai Wei SUN , Han Boon TEO , Jing Ya LI , Sughosh Pavan SHASHIDHAR , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC分类号： H04N19/46 , H04N19/159 , H04N19/176
摘要： An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.
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公开(公告)号：US20230007243A1
公开(公告)日：2023-01-05
申请号：US17943971
申请日：2022-09-13
发明人： Ru Ling LIAO , Chong Soon LIM , Hai Wei SUN , Han Boon TEO , Jing Ya LI , Sughosh Pavan SHASHIDHAR , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC分类号： H04N19/105 , H04N19/176 , H04N19/159
摘要： An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.
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公开(公告)号：US20220295060A1
公开(公告)日：2022-09-15
申请号：US17726125
申请日：2022-04-21
发明人： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC分类号： H04N19/119 , H04N19/176
摘要： Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.
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公开(公告)号：US20220248033A1
公开(公告)日：2022-08-04
申请号：US17726840
申请日：2022-04-22
发明人： Jing Ya LI , Ru Ling LIAO , Chong Soon LIM , Han Boon TEO , Hai Wei SUN , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC分类号： H04N19/159 , H04N19/117 , H04N19/182
摘要： An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of gradient values in first and second ranges; derives, as a first parameter, a total sum of absolute values of sums of gradient values derived respectively for pairs of relative pixel positions; derives a pixel difference value between pixel values in the first and second ranges; inverts or maintains a plus or minus sign of the pixel difference value, according to a plus or minus sign of the sum of the gradient values indicating the sum of the gradient values in the first and second ranges; derives, as a second parameter, a total sum of pixel difference values each having the plus or minus sign inverted or maintained, the pixel difference values derived respectively for the relative pixel positions; and generates a prediction image using the first and second parameters.
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公开(公告)号：US20220248015A1
公开(公告)日：2022-08-04
申请号：US17727201
申请日：2022-04-22
发明人： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC分类号： H04N19/119 , H04N19/176
摘要： Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.
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