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    ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD
    1.
    发明申请
    ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD 有权

    公开(公告)号：US20230138357A1

    公开(公告)日：2023-05-04

    申请号：US18090621

    申请日：2022-12-29

    申请人： Panasonic Intellectual Property Corporation of America

    发明人： Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Ryuichi KANOH

    IPC分类号： H04N19/31 ,  H04N19/117 ,  H04N19/172

    摘要： An encoder which encodes a video including a plurality of pictures includes circuitry and memory. Using the memory, the circuitry performs: encoding a first picture among the plurality of pictures; and performing (i) a first operation for encoding a parameter set for a second picture which follows the first picture in coding order among the plurality of pictures after encoding the first picture, and encoding the second picture after encoding the parameter set, or (ii) a second operation for encoding the second picture without encoding the parameter set after encoding the first picture. The circuitry performs the first operation when the second picture is a determined picture, in the performing of the first operation or the second operation.

    ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD
    2.
    发明申请
    ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD 有权

    公开(公告)号：US20230093946A1

    公开(公告)日：2023-03-30

    申请号：US18062455

    申请日：2022-12-06

    申请人： Panasonic Intellectual Property Corporation of America

    发明人： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

    IPC分类号： H04N19/117 ,  H04N19/136 ,  H04N19/82 ,  H04N19/176 ,  H04N19/182 ,  H04N19/61 ,  H04N19/159

    摘要： A decoder includes a memory and processing circuitry. The processing circuitry, in operation, changes values of pixels in a first block and a second block to filter a boundary therebetween, using clipping such that change amounts of the respective values are within respective clip widths. The clip widths for the pixels in the first block and the second block are selected based on block sizes of the first block and the second block. The pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary. The clip widths include a first clip width and a second clip width corresponding to the first pixel and the second pixel, respectively, and the first clip width is different from the second width.

    ENCODER, DECODER, ENCODING METHOD, DECODING METHOD, AND RECORDING MEDIUM
    4.
    发明申请
    ENCODER, DECODER, ENCODING METHOD, DECODING METHOD, AND RECORDING MEDIUM 有权

    公开(公告)号：US20220303572A1

    公开(公告)日：2022-09-22

    申请号：US17835743

    申请日：2022-06-08

    申请人： Panasonic Intellectual Property Corporation of America

    发明人： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Takashi HASHIMOTO

    IPC分类号： H04N19/52 ,  H04N19/105 ,  H04N19/176 ,  H04N19/59

    摘要： An encoder that; obtains two prediction images by performing motion compensation using two motion vectors; obtains a gradient value of each of pixels included in the two prediction images; derives a local motion estimation value for each of sub-blocks based on the pixel value and the gradient value of each of the pixels, the sub-blocks being obtained by partitioning the current block; and generates a final prediction image for the current block using the pixel value and the gradient value of each of the pixels, and the local motion estimation value derived for each of the sub-blocks. Each of the pixels in the two prediction images is interpolated with sub-pixel accuracy, and a reference range for the interpolation is included in a normal reference range that is referred to for motion compensation for the current block in normal inter prediction performed without using the local motion estimation value.

    ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD
    8.
    发明申请
    ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD 有权

    公开(公告)号：US20210227217A1

    公开(公告)日：2021-07-22

    申请号：US17227015

    申请日：2021-04-09

    申请人： Panasonic Intellectual Property Corporation of America

    发明人： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

    IPC分类号： H04N19/117 ,  H04N19/146 ,  H04N19/176

    摘要： A decoder comprises circuitry and memory. The circuitry, using the memory, in operation, determines a number of first pixels and a number of second pixels used in a deblocking filter process, wherein the first pixels are located at an upper side of a block boundary and the second pixels are located at a lower side of the block boundary, and performs the deblocking filter process on the block boundary. The number of the first pixels and the number of the second pixels are selected from among candidates, wherein the candidates include at least 4 and M larger than 4. Response to a location of the block boundary being a predetermined location, the number of the first pixels used in the deblocking filter process is limited to be 4.