Invention Publication
- Patent Title: PROCESS FOR REDUCING PATTERN-INDUCED WAFER DEFORMATION
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Application No.: US18096704Application Date: 2023-01-13
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Publication No.: US20230170314A1Publication Date: 2023-06-01
- Inventor: Jonas Höhenberger , Gernot Biese
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- The original application number of the division: US17030310 2020.09.23
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/544 ; H01L21/76
Abstract:
A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.
Information query
IPC分类:
