公开(公告)号：US20210091013A1

公开(公告)日：2021-03-25

申请号：US17030310

申请日：2020-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonas Höhenberger ,  Gernot Biese

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/76

Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.

公开(公告)号：US11587889B2

公开(公告)日：2023-02-21

申请号：US17030310

申请日：2020-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonas Höhenberger ,  Gernot Biese

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/76

Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.

公开(公告)号：US20250120157A1

公开(公告)日：2025-04-10

申请号：US18610150

申请日：2024-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonas Höhenberger ,  Ujwal Radhakrishna ,  Michael Lueders ,  Meng-Chia Lee ,  Chang Soo Suh ,  Zhikai Tang ,  Jungwoo Joh ,  Timothy Bryan Merkin ,  Stefan Herzer ,  Bernhard Ziegltrum ,  Helmut Rinck ,  Michael Hans Enzelberger-Heim ,  Ercuement Hasanoglu

IPC: H01L29/40 ,  H01L21/027 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure generally relates to a semiconductor device having a slanted field plate. In an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on a surface of the semiconductor substrate. The drain contact and a source contact are on the semiconductor substrate. The field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. The field plate includes multiple field plate portions. Each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.

公开(公告)号：US20250105135A1

公开(公告)日：2025-03-27

申请号：US18472837

申请日：2023-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonas Höhenberger ,  Michael Hans Enzelberger-Heim

IPC: H01L23/522 ,  H01L27/06

Abstract: The present disclosure generally relates to a corrugated capacitor in an integrated circuit (IC). In an example, an IC includes a first corrugated conductive layer, a second corrugated conductive layer, and a corrugated dielectric layer. The first corrugated conductive layer and the second corrugated conductive layer are over a semiconductor substrate. The corrugated dielectric layer is between the first corrugated conductive layer and the second corrugated conductive layer. Various examples may achieve a larger surface areas for respective plates of a capacitor for a given lateral footprint of the capacitor.

公开(公告)号：US11869725B2

公开(公告)日：2024-01-09

申请号：US17537626

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Michael Hans Enzelberger-Heim ,  Jonas Höhenberger

IPC: H01G4/40 ,  H01G4/008 ,  H01G4/30

CPC classification number: H01G4/40 ,  H01G4/008 ,  H01G4/30

Abstract: A stacked capacitor includes a capacitor stack. The capacitor stack includes a base plate having a first surface and a second opposing surface, a first dielectric layer on or over the base plate, and a first conductive plate on or over the first dielectric layer. A second dielectric layer is on or over the first conductive plate. A second conductive plate on or over the second dielectric layer. The capacitor stack has at least one sloped side with at least one slope with respect to the second surface of the base plate.

公开(公告)号：US20230170314A1

公开(公告)日：2023-06-01

申请号：US18096704

申请日：2023-01-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonas Höhenberger ,  Gernot Biese

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/76

CPC classification number: H01L23/564 ,  H01L23/544 ,  H01L21/76 ,  H01L2223/5446 ,  H01L2223/54406 ,  H01L2223/54426

Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.