A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.