公开(公告)号：US20230214124A1

公开(公告)日：2023-07-06

申请号：US17934691

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Sukhan Lee ,  Kyomin Sohn

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0673

Abstract: A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.

公开(公告)号：US20230128183A1

公开(公告)日：2023-04-27

申请号：US17938789

申请日：2022-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhaeng Kang ,  Sukhan Lee ,  Hweesoo Kim ,  Kyomin Sohn

IPC: G06F3/06

Abstract: A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.

公开(公告)号：US11513770B2

公开(公告)日：2022-11-29

申请号：US16909214

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Sukhan Lee

IPC: G06F7/487 ,  G06F7/544 ,  G06F5/01 ,  G06F9/30

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

公开(公告)号：US11494121B2

公开(公告)日：2022-11-08

申请号：US17098959

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan Ro ,  Shinhaeng Kang ,  Seongwook Park ,  Seungwoo Seo

IPC: G06F3/06 ,  G06N3/063 ,  G06F7/523

Abstract: A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.

公开(公告)号：US12230345B2

公开(公告)日：2025-02-18

申请号：US18059462

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Park ,  Shinhaeng Kang

IPC: G11C29/12 ,  G06F11/00 ,  G11C29/28 ,  G11C29/36

Abstract: A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.

公开(公告)号：US12099455B2

公开(公告)日：2024-09-24

申请号：US17591928

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-soo Yu ,  Shinhaeng Kang ,  Yuhwan Ro

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/38 ,  G06F13/40 ,  G06F15/78 ,  G11C7/18 ,  G11C8/14

CPC classification number: G06F13/1668 ,  G06F9/3016

Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

公开(公告)号：US11830562B2

公开(公告)日：2023-11-28

申请号：US17840722

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Joonho Song ,  Seungwon Lee

IPC: G11C29/38 ,  G06F11/20 ,  G06F12/0815 ,  H01L25/065 ,  H01L25/18 ,  G11C29/00 ,  G01R31/3193

CPC classification number: G11C29/38 ,  G01R31/3193 ,  G06F11/2094 ,  G06F12/0815 ,  G11C29/765 ,  G11C29/808 ,  H01L25/0657 ,  H01L25/18 ,  G06F2201/82 ,  G06F2212/1032 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

公开(公告)号：US20230178166A1

公开(公告)日：2023-06-08

申请号：US18059462

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Park ,  Shinhaeng Kang

IPC: G11C29/12 ,  G11C29/28 ,  G11C29/36

CPC classification number: G11C29/1201 ,  G11C29/28 ,  G11C29/36 ,  G11C2029/3602

Abstract: A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.

公开(公告)号：US11094371B2

公开(公告)日：2021-08-17

申请号：US16810344

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Shinhaeng Kang ,  Namsung Kim ,  Kyomin Sohn ,  Sukhan Lee

IPC: G11C11/409 ,  G11C11/4096 ,  G06N3/063 ,  G06N3/04 ,  G06F13/16

Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.

公开(公告)号：US12204796B2

公开(公告)日：2025-01-21

申请号：US17954532

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan Ro ,  Shinhaeng Kang ,  Seongwook Park ,  Seungwoo Seo

IPC: G06F3/06 ,  G06F7/523 ,  G06N3/063

Abstract: A memory device includes: memory operation circuitries to perform memory processing; memory banks assigned to one of the memory operation circuitries such that a set of n memory banks is assigned to each of the memory operation circuitries; and command pads to receive a command signal from an external source, wherein, for each of the memory operation circuitries, a corresponding memory operation circuitry to access memory banks of a corresponding set of n memory banks that is assigned to the corresponding memory operation circuitry, in an order determined based on respective distances from each of the memory banks of the corresponding set of n memory banks to the command pads, and wherein, each of the memory banks of the corresponding set of n memory banks to perform an access operation of data requested by the corresponding memory operation circuitry while the memory processing is performed.