Invention Publication
- Patent Title: INTEGRATED CIRCUIT STRUCTURES INCLUDING ELASTROSTATIC DISCHARGE BALLASTING RESISTOR BASED ON BURIED POWER RAIL
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Application No.: US17540609Application Date: 2021-12-02
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Publication No.: US20230178542A1Publication Date: 2023-06-08
- Inventor: Harald Gossner , Georgios Panagopoulos , Johannes Xaver Rauh , Richard Geiger
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L23/48

Abstract:
IC structures including BPRs used for ESD ballasting are disclosed. An IC structure includes semiconductor structures of one or more transistors. A semiconductor structure may be a fin, nanowire, or nanoribbon of a semiconductor material. The IC structure also includes an electrically conductive layer coupled to the semiconductor structures, a power rail, and a support structure. The power rail is coupled to the electrically conductive layer by a via. The power rail is buried in a support structure. The combination of the power rail and the via constitutes a ESD ballasting resistor for the semiconductor structures. A resistance of the ESD ballasting resistor can be in a range from 5 to 20 ohms. The IC structure may include two or more power rails. A power rail may be arranged between two of the semiconductor structures. The power rails may form a meander structure with other components of the IC structure.
Information query
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