公开(公告)号：US20230187313A1

公开(公告)日：2023-06-15

申请号：US17550335

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Richard Geiger ,  Alexander Bechtold ,  Uwe Hodel ,  Richard Hudeczek ,  Walther Lutz ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: H01L23/48 ,  H01L23/66 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L23/66 ,  H01L23/5286 ,  H01L27/0886 ,  H01L2223/6616

Abstract: IC devices including transmission lines are disclosed. An example IC device includes two electrically conductive layers (first and second layers) and a support structure between the two electrically conductive layers. The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission is placed in the first layer. Conductors of the transmission line are placed in the second layer and are coupled to the first layer by TSVs. Another example IC device includes three electrically conductive layers (first, second, and third layers). The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission line is placed in the second layer and conductors of the transmission line are placed in the third layer. The conductors are coupled to the first layer by TSVs and coupled to the second layer by vias.

公开(公告)号：US20250006719A1

公开(公告)日：2025-01-02

申请号：US18341875

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Georgios Panagopoulos ,  Richard Geiger ,  Steven Callender ,  Georgios Dogiamis ,  Manisha Dutta ,  Stefano Pellerano

IPC: H01L25/18 ,  H01L23/00 ,  H01Q1/22 ,  H01Q23/00

Abstract: Example antenna module includes antenna units provided over an antenna unit support, and ICs communicatively coupled to various antenna units. The ICs are arranged in two or more subsets of one or more ICs in each subset, where an individual IC belongs to only one subset, different subsets are in different layers with respect to the antenna unit support, and an average pitch of projections of all of the ICs onto a plane parallel to the antenna unit support is substantially equal to, or smaller, than an average pitch of the antenna units. When an average width of the ICs is larger than the average pitch of the antenna units, arranging the ICs in two or more subsets in different layers means that at least one of the ICs of one subset partially overlaps with at least one of the ICs of another subset.

公开(公告)号：US20230197598A1

公开(公告)日：2023-06-22

申请号：US17554004

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Georgios Panagopoulos ,  Richard Geiger ,  Peter Baumgartner ,  Harald Gossner ,  Uwe Hodel ,  Michael Langenbuch ,  Johannes Xaver Rauh ,  Alexander Bechtold ,  Richard Hudeczek ,  Carla Moran Guizan

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including inductors or transformers formed based on BPRs are disclosed. An example IC device includes semiconductor structures of one or more transistors, an electrically conductive layer, a support structure comprising a semiconductor material, and an inductor. The inductor includes an electrical conductor constituted by a power rail buried in the support structure. The inductor also includes a magnetic core coupled to the electrical conductor. The magnetic core includes magnetic rails buried in the support structure, magnetic TSVs buried in the support structure, and a magnetic plate at the backside of the support structure. The magnetic core includes a magnetic material, such as Fe, NiFe, CoZrTa, etc. In some embodiments, the IC device includes another power rail that is buried in the support structure and constitutes another electrical conductor coupled to the magnetic core. The two power rails and magnetic core can constitute a transformer.

公开(公告)号：US20230252214A1

公开(公告)日：2023-08-10

申请号：US17666616

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Richard Hudeczek ,  Carla Moran Guizan ,  Peter Baumgartner ,  Richard Geiger ,  Alexander Bechtold ,  Uwe Hodel ,  Walther Lutz ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: G06F30/392 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L27/0207

Abstract: Methods for providing fill patterns for IC devices are disclosed. An example method includes detecting a first device and a second device in an image, e.g., a two- or three-dimensional image representing the IC device. A line is defined based on the devices. The line divides the image into a first section and a second section. A first structure is generated based on the first device. A second structure is generated based on the second device. The second structure is a mirror image of the first structure across the line. A first fill pattern is generated in the first section based on the first structure. A second fill pattern is generated in the second section based on the first fill pattern, e.g., through a reflection transformation of the first fill pattern across the line. The two fill patterns represent patterns of fill structures to be included in the IC device.

公开(公告)号：US20230187300A1

公开(公告)日：2023-06-15

申请号：US17549137

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Harald Gossner

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/481 ,  H01L23/5286

Abstract: IC devices including BHRs and TSVs for backside heat dissipation are disclosed. An example IC device includes semiconductor structures. The IC device also includes an electrically conductive layer coupled to the semiconductor structures. The IC device further includes one or more BHRs coupled to the electrically conductive layer. Each BHR is connected to a heat dissipation plate by a TSV buried in a support structure. The heat dissipation plate is at the backside of the support structure. The BHRs, TSVs, and heat dissipation plate can conduct heat generated by the semiconductor structures to the backside of the support structure. The BHRs may also be used as power rails for delivering power to the semiconductor structures. A TSV can be enlarged to have a larger cross-sectional area than the BHR for enhancing the heat dissipation. Also, the heat dissipation plate may exceed a cell boundary for sinking heat more efficiently.

公开(公告)号：US20230178542A1

公开(公告)日：2023-06-08

申请号：US17540609

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Richard Geiger

IPC: H01L27/02 ,  H01L23/48

CPC classification number: H01L27/0292 ,  H01L27/0288 ,  H01L23/481 ,  H01L27/0886

Abstract: IC structures including BPRs used for ESD ballasting are disclosed. An IC structure includes semiconductor structures of one or more transistors. A semiconductor structure may be a fin, nanowire, or nanoribbon of a semiconductor material. The IC structure also includes an electrically conductive layer coupled to the semiconductor structures, a power rail, and a support structure. The power rail is coupled to the electrically conductive layer by a via. The power rail is buried in a support structure. The combination of the power rail and the via constitutes a ESD ballasting resistor for the semiconductor structures. A resistance of the ESD ballasting resistor can be in a range from 5 to 20 ohms. The IC structure may include two or more power rails. A power rail may be arranged between two of the semiconductor structures. The power rails may form a meander structure with other components of the IC structure.

公开(公告)号：US20230068318A1

公开(公告)日：2023-03-02

申请号：US17459986

申请日：2021-08-27

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Luis Felipe Giles ,  Peter Baumgartner ,  Harald Gossner ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then

IPC: H01L29/207 ,  H01L29/20 ,  H01L27/06 ,  H01L29/66

Abstract: Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×1017 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 1017 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

公开(公告)号：US09514796B1

公开(公告)日：2016-12-06

申请号：US14751801

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Shigeki Tomishima ,  Wei Wu ,  Shih-Lien Lu ,  James W. Tschanz ,  Georgios Panagopoulos ,  Helia Naeimi

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Abstract translation: 描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。 该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。 该装置还包括用于迭代地写入一个或多个比特位置的电路​​，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。

公开(公告)号：US20230207464A1

公开(公告)日：2023-06-29

申请号：US17552683

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Harald Gossner

IPC: H01L23/528

CPC classification number: H01L23/5286

Abstract: IC devices including IC devices including BPRs that form metal-semiconductor junctions with semiconductor sections where the BPRs are partially buried are disclosed. An example IC device includes a first layer comprising semiconductor structures, such as fins, nanowires, or nanoribbons. The IC device also includes a layer comprising an electrically conductive material and coupled to the semiconductor structures. The IC device further includes a support structure comprising a BPR and a semiconductor section. The BPR contacts with the semiconductor section and forms a metal-semiconductor junction. The metal-semiconductor junction constitutes a Schottky barrier for electrons. The IC device may include a SCR including a sequence of p-well, n-well, p-well, and n-well with Schottky barriers in the first p-well and the second n-well. The Schottky barrier may also be used as a guard ring to extract injected charge carriers.

公开(公告)号：US20230197527A1

公开(公告)日：2023-06-22

申请号：US17554061

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Peter Baumgartner ,  Alexander Bechtold ,  Uwe Hodel ,  Richard Hudeczek ,  Walther Lutz ,  Carla Moran Guizan ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/823821 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/5226 ,  H01L27/0924

Abstract: IC devices including semiconductor devices isolated by BSRs are disclosed. An example IC device includes a first and a second semiconductor devices, a support structure, and a BSR. The BSR defines boundaries of a first and second section in the support structure. At least a portion of the first semiconductor device is in the first section, and at least a portion of the second semiconductor device is in the second section. The first semiconductor device is isolated from the second semiconductor device by the BSR. Signals from the first semiconductor device would not be transmitted to the second semiconductor device through the support structure. The BSR may be connected to a TSV or be biased. The IC device may include additional BSRs to isolate the first and second semiconductor devices. An BSR may be a power rail used for delivering power.