公开(公告)号：US20230187313A1

公开(公告)日：2023-06-15

申请号：US17550335

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Richard Geiger ,  Alexander Bechtold ,  Uwe Hodel ,  Richard Hudeczek ,  Walther Lutz ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: H01L23/48 ,  H01L23/66 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L23/66 ,  H01L23/5286 ,  H01L27/0886 ,  H01L2223/6616

Abstract: IC devices including transmission lines are disclosed. An example IC device includes two electrically conductive layers (first and second layers) and a support structure between the two electrically conductive layers. The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission is placed in the first layer. Conductors of the transmission line are placed in the second layer and are coupled to the first layer by TSVs. Another example IC device includes three electrically conductive layers (first, second, and third layers). The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission line is placed in the second layer and conductors of the transmission line are placed in the third layer. The conductors are coupled to the first layer by TSVs and coupled to the second layer by vias.

公开(公告)号：US11545586B2

公开(公告)日：2023-01-03

申请号：US16643929

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

公开(公告)号：US11373995B2

公开(公告)日：2022-06-28

申请号：US16643928

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L27/02 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66 ,  H01L29/872 ,  H01L27/07

Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure,
an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230252214A1

公开(公告)日：2023-08-10

申请号：US17666616

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Richard Hudeczek ,  Carla Moran Guizan ,  Peter Baumgartner ,  Richard Geiger ,  Alexander Bechtold ,  Uwe Hodel ,  Walther Lutz ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: G06F30/392 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L27/0207

Abstract: Methods for providing fill patterns for IC devices are disclosed. An example method includes detecting a first device and a second device in an image, e.g., a two- or three-dimensional image representing the IC device. A line is defined based on the devices. The line divides the image into a first section and a second section. A first structure is generated based on the first device. A second structure is generated based on the second device. The second structure is a mirror image of the first structure across the line. A first fill pattern is generated in the first section based on the first structure. A second fill pattern is generated in the second section based on the first fill pattern, e.g., through a reflection transformation of the first fill pattern across the line. The two fill patterns represent patterns of fill structures to be included in the IC device.

公开(公告)号：US20230187300A1

公开(公告)日：2023-06-15

申请号：US17549137

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Harald Gossner

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/481 ,  H01L23/5286

Abstract: IC devices including BHRs and TSVs for backside heat dissipation are disclosed. An example IC device includes semiconductor structures. The IC device also includes an electrically conductive layer coupled to the semiconductor structures. The IC device further includes one or more BHRs coupled to the electrically conductive layer. Each BHR is connected to a heat dissipation plate by a TSV buried in a support structure. The heat dissipation plate is at the backside of the support structure. The BHRs, TSVs, and heat dissipation plate can conduct heat generated by the semiconductor structures to the backside of the support structure. The BHRs may also be used as power rails for delivering power to the semiconductor structures. A TSV can be enlarged to have a larger cross-sectional area than the BHR for enhancing the heat dissipation. Also, the heat dissipation plate may exceed a cell boundary for sinking heat more efficiently.

公开(公告)号：US20220320350A1

公开(公告)日：2022-10-06

申请号：US17848275

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US11201151B2

公开(公告)日：2021-12-14

申请号：US16833094

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Richard Hudeczek ,  Philipp Riess ,  Richard Geiger ,  Peter Baumgartner

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.

公开(公告)号：US20230178542A1

公开(公告)日：2023-06-08

申请号：US17540609

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Richard Geiger

IPC: H01L27/02 ,  H01L23/48

CPC classification number: H01L27/0292 ,  H01L27/0288 ,  H01L23/481 ,  H01L27/0886

Abstract: IC structures including BPRs used for ESD ballasting are disclosed. An IC structure includes semiconductor structures of one or more transistors. A semiconductor structure may be a fin, nanowire, or nanoribbon of a semiconductor material. The IC structure also includes an electrically conductive layer coupled to the semiconductor structures, a power rail, and a support structure. The power rail is coupled to the electrically conductive layer by a via. The power rail is buried in a support structure. The combination of the power rail and the via constitutes a ESD ballasting resistor for the semiconductor structures. A resistance of the ESD ballasting resistor can be in a range from 5 to 20 ohms. The IC structure may include two or more power rails. A power rail may be arranged between two of the semiconductor structures. The power rails may form a meander structure with other components of the IC structure.

公开(公告)号：US20230068318A1

公开(公告)日：2023-03-02

申请号：US17459986

申请日：2021-08-27

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Luis Felipe Giles ,  Peter Baumgartner ,  Harald Gossner ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then

IPC: H01L29/207 ,  H01L29/20 ,  H01L27/06 ,  H01L29/66

Abstract: Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×1017 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 1017 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

公开(公告)号：US20250006719A1

公开(公告)日：2025-01-02

申请号：US18341875

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Georgios Panagopoulos ,  Richard Geiger ,  Steven Callender ,  Georgios Dogiamis ,  Manisha Dutta ,  Stefano Pellerano

IPC: H01L25/18 ,  H01L23/00 ,  H01Q1/22 ,  H01Q23/00

Abstract: Example antenna module includes antenna units provided over an antenna unit support, and ICs communicatively coupled to various antenna units. The ICs are arranged in two or more subsets of one or more ICs in each subset, where an individual IC belongs to only one subset, different subsets are in different layers with respect to the antenna unit support, and an average pitch of projections of all of the ICs onto a plane parallel to the antenna unit support is substantially equal to, or smaller, than an average pitch of the antenna units. When an average width of the ICs is larger than the average pitch of the antenna units, arranging the ICs in two or more subsets in different layers means that at least one of the ICs of one subset partially overlaps with at least one of the ICs of another subset.