Invention Publication
- Patent Title: SOURCE OR DRAIN METALLIZATION PRIOR TO CONTACT FORMATION IN STACKED TRANSISTORS
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Application No.: US17556748Application Date: 2021-12-20
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Publication No.: US20230197777A1Publication Date: 2023-06-22
- Inventor: Gilbert Dewey , Cheng-Ying Huang , Nicole K. Thomas , Marko Radosavljevic , Patrick Morrow , Ashish Agrawal , Willy Rachmady , Nazila Haratipour , Seung Hoon Sung , I-Cheng Tung , Christopher M. Neumann , Koustav Ganguly , Subrina Rafique
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/423 ; H01L29/786

Abstract:
Techniques are provided herein to form gate-all-around (GAA) semiconductor devices utilizing a metal fill in an epi region of a stacked transistor configuration. In one example, an n-channel device and the p-channel device may both be GAA transistors each having any number of nanoribbons extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. A metal fill may be provided around the source or drain region of the bottom semiconductor device to provide a high contact area between the highly conductive metal fill and the epitaxial material of that source or drain region. Metal fill may also be used around the top source or drain region to further improve conductivity throughout both of the stacked source or drain regions.
Information query
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