公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

申请人： Intel Corporation

发明人： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

摘要： In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US11777029B2

公开(公告)日：2023-10-03

申请号：US16455567

申请日：2019-06-27

申请人： Intel Corporation

发明人： Nazila Haratipour ,  I-Cheng Tung ,  Abhishek A. Sharma ,  Arnab Sen Gupta ,  Van Le ,  Matthew V. Metz ,  Jack Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/42364 ,  H01L29/66666

摘要： A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.

公开(公告)号：US20230253444A1

公开(公告)日：2023-08-10

申请号：US17666745

申请日：2022-02-08

申请人： Intel Corporation

发明人： Arnab Sen Gupta ,  Kaan Oguz ,  Chia-Ching Lin ,  I-Cheng Tung ,  Sudarat Lee ,  Sou-Chi Chang ,  Matthew V. Metz ,  Scott B. Clendenning ,  Uygar E. Avci ,  Ian A. Young ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC分类号： H01L49/02 ,  H01L27/108

CPC分类号： H01L28/65 ,  H01L28/75 ,  H01L27/10829

摘要： Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

公开(公告)号：US20210408018A1

公开(公告)日：2021-12-30

申请号：US16914140

申请日：2020-06-26

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC分类号： H01L27/11502 ,  H01L49/02 ,  H01L27/08 ,  H01G4/008 ,  G11C11/22

摘要： An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US11980037B2

公开(公告)日：2024-05-07

申请号：US16906217

申请日：2020-06-19

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Jack T. Kavalieros ,  Uygar E. Avci ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Devin R. Merrill ,  Matthew V. Metz ,  I-Cheng Tung

IPC分类号： H10B53/30 ,  H01L21/768 ,  H01L23/522

CPC分类号： H10B53/30 ,  H01L21/7687 ,  H01L23/5226 ,  H01L21/76843

摘要： Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC分类号： H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

摘要： Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.

公开(公告)号：US11742407B2

公开(公告)日：2023-08-29

申请号：US16700757

申请日：2019-12-02

申请人： Intel Corporation

发明人： Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Sou-Chi Chang ,  Devin Merrill ,  I-Cheng Tung ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Ian A. Young ,  Matthew V. Metz ,  Uygar E. Avci ,  Chia-Ching Lin ,  Owen Loh ,  Shriram Shivaraman ,  Eric Charles Mattson

IPC分类号： H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/512 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7851

摘要： A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20230197728A1

公开(公告)日：2023-06-22

申请号：US17554791

申请日：2021-12-17

申请人： Intel Corporation

发明人： Nicole K. Thomas ,  Eric Mattson ,  Sudarat Lee ,  Sarah Atanasov ,  Christopher J. Jezewski ,  Charles Mokhtarzadeh ,  Thoe Michaelos ,  I-Cheng Tung ,  Charles C. Kuo ,  Scott B. Clendenning ,  Matthew V. Metz

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

摘要： An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.

公开(公告)号：US20220181433A1

公开(公告)日：2022-06-09

申请号：US17116315

申请日：2020-12-09

申请人： Intel Corporation

发明人： Sou-Chi Chang ,  Chia-Ching Lin ,  Kaan Oguz ,  I-Cheng Tung ,  Uygar E. Avci ,  Matthew V. Metz ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Arnab Sen Gupta

IPC分类号： H01L49/02

摘要： Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

公开(公告)号：US20240105508A1

公开(公告)日：2024-03-28

申请号：US17935647

申请日：2022-09-27

申请人： Intel Corporation

发明人： Jitendra Kumar Jha ,  Justin Mueller ,  Nazila Haratipour ,  Gilbert W. Dewey ,  Chi-Hing Choi ,  Jack T. Kavalieros ,  Siddharth Chouksey ,  Nancy Zelick ,  Jean-Philippe Turmaud ,  I-Cheng Tung ,  Blake Bluestein

IPC分类号： H01L21/768 ,  H01L29/49

CPC分类号： H01L21/76856 ,  H01L21/76837 ,  H01L21/76877 ,  H01L29/4908

摘要： Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.